/external/mesa3d/src/mesa/sparc/ |
sparc_matrix.h | 39 #define M4 %f20
|
/external/v8/test/mjsunit/harmony/ |
block-let-crankshaft.js | 34 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26, 135 function f20() { function
|
/external/valgrind/none/tests/mips32/ |
MoveIns.stdout.exp | 22 mfc1 $a3, $f20 :: fs 0.000000, rt 0x0 50 mtc1 $a3, $f20 :: fs 0.000000, rt 0x0 78 mov.s $f19, $f20 :: fs -1.000000, rt 0xbf800000 79 mov.s $f20, $f21 :: fs 1384.599976, rt 0x44ad1333 105 mov.d $f18, $f20 ::fs -0.007813, rt 0x40400000 106 mov.d $f18, $f20 ::fs -52072.789633, rt 0x44ad1333 107 mov.d $f20, $f22 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28 108 mov.d $f20, $f22 ::fs 0.000000, rt 0x44db0000
|
/external/llvm/test/MC/Mips/mips1/ |
invalid-mips2.s | 21 ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
invalid-mips4.s | 13 ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 62 movn.d $f26,$f20,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
invalid-mips3.s | 13 ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
invalid-mips5.s | 13 ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
/external/llvm/test/MC/Mips/ |
mips-fpu-instructions.s | 170 # CHECK: lwxc1 $f20, $12($14) # encoding: [0x00,0x05,0xcc,0x4d] 205 lwxc1 $f20, $12($14)
|
/external/v8/src/mips/ |
simulator-mips.h | 145 f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, enumerator in enum:v8::internal::Simulator::FPURegister
|
assembler-mips.h | 307 const FPURegister f20 = { 20 }; member in namespace:v8::internal [all...] |
/external/clang/test/CodeGen/ |
arm64-arguments.c | 84 // CHECK: define i64 @f20() 86 struct s20 f20(void) {} function
|
/external/libunwind/src/ia64/ |
Ginstall_cursor.S | 96 ldf.fill f20 = [r20] // f20 restored (don't touch no more)
|
/external/v8/src/mips64/ |
simulator-mips64.h | 174 f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, enumerator in enum:v8::internal::Simulator::FPURegister
|
assembler-mips64.h | 298 const FPURegister f20 = { 20 }; member in namespace:v8::internal [all...] |
/external/jmonkeyengine/engine/src/core/com/jme3/math/ |
Matrix3f.java | 996 float f20 = m10 * m21 - m11 * m20; local 1006 m20 = f20; [all...] |
Matrix4f.java | 1500 float f20 = +m10 * fB4 - m11 * fB2 + m13 * fB0; local [all...] |
/external/llvm/test/MC/Mips/mips2/ |
invalid-mips32r2.s | 25 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
/external/valgrind/memcheck/ |
mc_machine.c | [all...] |
/external/valgrind/memcheck/tests/ |
deep-backtrace.c | 20 int f20(int *p) { return f19(p); } function 21 int f21(int *p) { return f20(p); }
|
/external/elfutils/src/tests/ |
run-allregs.sh | 211 52: f20 (f20), float 64 bits [all...] |
/external/libcxxabi/src/Unwind/ |
UnwindRegistersRestore.S | 161 lfd f20,320(r3)
|
UnwindRegistersSave.S | 165 stfd f20,320(r3)
|
/ndk/sources/cxx-stl/llvm-libc++abi/libcxxabi/src/Unwind/ |
UnwindRegistersRestore.S | 161 lfd f20,320(r3)
|
UnwindRegistersSave.S | 165 stfd f20,320(r3)
|
/art/runtime/arch/mips/ |
quick_entrypoints_mips.S | 76 SDu $f20, $f21, 4, $sp, $t1 335 LDu $f20, $f21, 10*8, $a1, $t1 [all...] |