| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 47 c.sf.s $f14,$f22
54 cvt.d.s $f22,$f28
57 cvt.s.w $f22,$f15
154 sqrt.d $f17,$f22
169 sub.s $f23,$f22,$f22
200 trunc.w.d $f22,$f15
|
| /external/clang/test/CodeGen/ |
| arm-arguments.c | 124 // APCS-GNU-LABEL: define i16 @f22()
130 // AAPCS-LABEL: define arm_aapcscc i16 @f22()
136 _Complex char f22(void) {} function
|
| x86_32-arguments-darwin.c | 100 // CHECK: void @f22(%{{.*}}* noalias sret %agg.result)
106 struct { T16 a; } f22(void) { while (1) {} } function
|
| x86_64-arguments.c | 127 void f22(L x, L y) { } function
128 // CHECK: @f22
|
| /external/clang/test/CodeGenCXX/ |
| debug-info-line.cpp | 266 void f22() { function
|
| /bionic/libc/arch-mips/bionic/ |
| setjmp.S | 155 #define SC_FPREGS_SAVED 6 /* even fp regs f20,f22,f24,f26,f28,f30 */
238 # the even-numbered double fp regs $f20,$f22,...$f30
240 s.d $f22, SC_FPREGS+1*REGSZ_FP(a0)
336 # the even-numbered double fp regs $f20,$f22,...$f30
338 l.d $f22, SC_FPREGS+1*REGSZ_FP(a0)
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 47 c.sf.s $f14,$f22
55 cvt.d.s $f22,$f28
61 cvt.s.w $f22,$f15
142 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
214 sqrt.d $f17,$f22
229 sub.s $f23,$f22,$f22
262 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 47 c.sf.s $f14,$f22
55 cvt.d.s $f22,$f28
61 cvt.s.w $f22,$f15
143 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
215 sqrt.d $f17,$f22
230 sub.s $f23,$f22,$f22
264 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 47 c.sf.s $f14,$f22
57 cvt.d.s $f22,$f28
63 cvt.s.w $f22,$f15
152 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
231 sqrt.d $f17,$f22
246 sub.s $f23,$f22,$f22
281 trunc.w.d $f22,$f15
|
| /external/valgrind/none/tests/mips32/ |
| MoveIns.c | 305 TESTINSNMOVE("mfc1 $v1, $f22", 20, f22, v1);
334 TESTINSNMOVEt("mtc1 $v1, $f22", 22, f22, v1);
363 TESTINSNMOVE1s("mov.s $f21, $f22", 20, f21, f22);
364 TESTINSNMOVE1s("mov.s $f22, $f23", 24, f22, f23);
391 TESTINSNMOVE1d("mov.d $f20, $f22", 24, f20, f22);
[all...] |
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 43 c.sf.s $f14,$f22
51 cvt.d.s $f22,$f28
57 cvt.s.w $f22,$f15
186 sqrt.d $f17,$f22
201 sub.s $f23,$f22,$f22
233 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 47 c.sf.s $f14,$f22
54 cvt.d.s $f22,$f28
59 cvt.s.w $f22,$f15
189 sqrt.d $f17,$f22
204 sub.s $f23,$f22,$f22
237 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 47 c.sf.s $f14,$f22
54 cvt.d.s $f22,$f28
59 cvt.s.w $f22,$f15
189 sqrt.d $f17,$f22
204 sub.s $f23,$f22,$f22
237 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 47 c.sf.s $f14,$f22
54 cvt.d.s $f22,$f28
59 cvt.s.w $f22,$f15
189 sqrt.d $f17,$f22
204 sub.s $f23,$f22,$f22
237 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 47 c.sf.s $f14,$f22
57 cvt.d.s $f22,$f28
63 cvt.s.w $f22,$f15
257 sqrt.d $f17,$f22
272 sub.s $f23,$f22,$f22
307 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 47 c.sf.s $f14,$f22
57 cvt.d.s $f22,$f28
63 cvt.s.w $f22,$f15
257 sqrt.d $f17,$f22
272 sub.s $f23,$f22,$f22
307 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 47 c.sf.s $f14,$f22
57 cvt.d.s $f22,$f28
63 cvt.s.w $f22,$f15
257 sqrt.d $f17,$f22
272 sub.s $f23,$f22,$f22
307 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/ELF/ |
| cfi.s | 131 f22: label
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips2.s | 26 sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
46 trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips3.s | 58 sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
68 trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips1.s | 14 c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips1.s | 17 c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/clang/test/Analysis/ |
| dead-stores.c | 241 void f22() { function
|
| /external/libunwind/src/ia64/ |
| getcontext.S | 156 stf.spill [r8] = f22, (FR(25) - FR(22)) // M3
|
| /external/mesa3d/src/mesa/sparc/ |
| sparc_matrix.h | 41 #define M6 %f22
|
