HomeSort by relevance Sort by last modified time
    Searched refs:f23 (Results 26 - 50 of 76) sorted by null

12 3 4

  /external/llvm/test/MC/PowerPC/
ppc64-regs.s 63 #CHECK: .cfi_offset f23, 492
180 .cfi_offset f23,492
  /external/llvm/test/MC/Mips/mips1/
invalid-mips4.s 59 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
60 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
86 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
invalid-mips5.s 58 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
59 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
84 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
invalid-mips3.s 66 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/llvm/test/MC/Mips/mips32r6/
invalid-mips32.s 16 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/clang/test/Analysis/
dead-stores.c 394 void f23(int argc, char **argv) { function
  /external/clang/test/CodeGen/
x86_32-arguments-darwin.c 110 // CHECK: float @f23()
113 struct { float a; } f23(void) { while (1) {} } function
x86_64-arguments.c 142 void f23(int A, struct f23S B) { function
143 // CHECK-LABEL: define void @f23(i32 %A, i64 %B.coerce0, i32 %B.coerce1)
arm64-arguments.c 93 // CHECK: define i64 @f23()
99 _Complex short f23(void) {} function
  /external/libunwind/src/ia64/
getcontext.S 158 stf.spill [r9] = f23, (FR(26) - FR(23)) // M2
  /external/llvm/test/MC/Mips/mips2/
invalid-mips3.s 52 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
invalid-mips32r2.s 35 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
36 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
  /external/llvm/test/MC/Mips/mips4/
valid.s 156 movf.s $f23,$f5,$fcc6
229 sub.s $f23,$f22,$f22
260 trunc.l.d $f23,$f23
  /external/llvm/test/MC/Mips/mips5/
valid.s 157 movf.s $f23,$f5,$fcc6
230 sub.s $f23,$f22,$f22
262 trunc.l.d $f23,$f23
  /external/llvm/test/MC/Mips/mips64/
valid.s 167 movf.s $f23,$f5,$fcc6
246 sub.s $f23,$f22,$f22
279 trunc.l.d $f23,$f23
  /external/llvm/test/MC/Mips/mips64r2/
valid.s 183 movf.s $f23,$f5,$fcc6
272 sub.s $f23,$f22,$f22
305 trunc.l.d $f23,$f23
  /external/llvm/test/MC/Mips/mips64r3/
valid.s 183 movf.s $f23,$f5,$fcc6
272 sub.s $f23,$f22,$f22
305 trunc.l.d $f23,$f23
  /external/llvm/test/MC/Mips/mips64r5/
valid.s 183 movf.s $f23,$f5,$fcc6
272 sub.s $f23,$f22,$f22
305 trunc.l.d $f23,$f23
  /external/mesa3d/src/mesa/sparc/
sparc_matrix.h 42 #define M7 %f23
  /external/v8/test/mjsunit/harmony/
block-let-crankshaft.js 34 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26,
153 function f23() { function
  /external/valgrind/none/tests/mips32/
MoveIns.c 306 TESTINSNMOVE("mfc1 $t8, $f23", 24, f23, t8);
335 TESTINSNMOVEt("mtc1 $t8, $f23", 26, f23, t8);
364 TESTINSNMOVE1s("mov.s $f22, $f23", 24, f22, f23);
365 TESTINSNMOVE1s("mov.s $f23, $f24", 28, f23, f24);
  /external/llvm/test/MC/Mips/mips32/
valid.s 103 movf.s $f23,$f5,$fcc6
169 sub.s $f23,$f22,$f22
  /external/llvm/test/MC/Mips/mips64r6/
invalid-mips64.s 28 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/v8/src/mips/
simulator-mips.h 145 f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, enumerator in enum:v8::internal::Simulator::FPURegister
  /external/llvm/test/MC/Mips/mips3/
valid.s 201 sub.s $f23,$f22,$f22
231 trunc.l.d $f23,$f23

Completed in 1467 milliseconds

12 3 4