| /external/llvm/test/MC/PowerPC/ |
| ppc64-regs.s | 65 #CHECK: .cfi_offset f25, 508
182 .cfi_offset f25,508
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 28 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 29 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32.s | 25 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 26 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
47 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
56 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 67 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
69 round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 66 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
68 round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 6 abs.d $f7,$f25 # CHECK: encoding:
50 ceil.w.d $f11,$f25
166 madd.s $f1,$f31,$f19,$f25
192 movz.s $f25,$f7,$v1
213 nmadd.s $f0,$f5,$f25,$f12
231 round.l.s $f25,$f5
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 6 abs.d $f7,$f25 # CHECK: encoding:
50 ceil.w.d $f11,$f25
166 madd.s $f1,$f31,$f19,$f25
192 movz.s $f25,$f7,$v1
213 nmadd.s $f0,$f5,$f25,$f12
231 round.l.s $f25,$f5
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 6 abs.d $f7,$f25 # CHECK: encoding:
50 ceil.w.d $f11,$f25
166 madd.s $f1,$f31,$f19,$f25
192 movz.s $f25,$f7,$v1
213 nmadd.s $f0,$f5,$f25,$f12
231 round.l.s $f25,$f5
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 6 abs.d $f7,$f25 # CHECK: encoding:
48 ceil.w.d $f11,$f25
103 madd.s $f1,$f31,$f19,$f25
127 movz.s $f25,$f7,$v1
150 nmadd.s $f0,$f5,$f25,$f12
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 6 abs.d $f7,$f25 # CHECK: encoding:
48 ceil.w.d $f11,$f25
103 madd.s $f1,$f31,$f19,$f25
127 movz.s $f25,$f7,$v1
150 nmadd.s $f0,$f5,$f25,$f12
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 6 abs.d $f7,$f25 # CHECK: encoding:
48 ceil.w.d $f11,$f25
103 madd.s $f1,$f31,$f19,$f25
127 movz.s $f25,$f7,$v1
150 nmadd.s $f0,$f5,$f25,$f12
|
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 6 abs.d $f7,$f25 # CHECK: encoding:
48 ceil.w.d $f11,$f25
112 movz.s $f25,$f7,$v1
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
71 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
73 round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
70 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
72 round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips3.s | 12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
55 round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /bionic/libc/arch-mips/bionic/ |
| setjmp.S | 153 #define SC_FPREGS_SAVED 8 /* all fp regs f24,f25,f26,f27,f28,f29,f30,f31 */
229 s.d $f25, SC_FPREGS+1*REGSZ_FP(a0)
327 l.d $f25, SC_FPREGS+1*REGSZ_FP(a0)
|
| /external/clang/test/Analysis/ |
| dead-stores.c | 446 int f25(int y) { function
455 // This test is mostly the same as 'f25', but shows that the heuristic of pruning out dead
|
| /external/clang/test/CodeGen/ |
| x86_32-arguments-darwin.c | 112 // CHECK: float @f25()
115 struct { struct {} a; struct { float a[1]; } b; } f25(void) { while (1) {} } function
|
| x86_64-arguments.c | 156 v4f32 f25(v4f32 X) { function
157 // CHECK-LABEL: define <4 x float> @f25(<4 x float> %X)
|
| /external/libunwind/src/ia64/ |
| getcontext.S | 159 stf.spill [r8] = f25, (FR(27) - FR(25)) // M3
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 6 abs.d $f7,$f25 # CHECK: encoding:
50 ceil.w.d $f11,$f25
165 movz.s $f25,$f7,$v1
192 round.l.s $f25,$f5
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 6 abs.d $f7,$f25 # CHECK: encoding:
50 ceil.w.d $f11,$f25
166 movz.s $f25,$f7,$v1
193 round.l.s $f25,$f5
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 6 abs.d $f7,$f25 # CHECK: encoding:
50 ceil.w.d $f11,$f25
176 movz.s $f25,$f7,$v1
207 round.l.s $f25,$f5
|
