| /external/libhevc/common/arm/ |
| ihevc_intra_pred_filters_chroma_mode_19_to_25.s | 271 add r10,r8,r9 @(i row)*pu1_ref[ref_main_idx]
273 vld1.8 {d8},[r10],r11 @(i row)ref_main_idx
276 vld1.8 {d9},[r10] @(i row)ref_main_idx_1
281 add r10,r8,r9 @(iii)*pu1_ref[ref_main_idx]
297 vld1.8 {d16},[r10],r11 @(iii)ref_main_idx
300 vld1.8 {d17},[r10] @(iii)ref_main_idx_1
320 add r10,r8,r9 @(v)*pu1_ref[ref_main_idx]
322 vld1.8 {d8},[r10],r11 @(v)ref_main_idx
328 vld1.8 {d9},[r10] @(v)ref_main_idx_1
339 add r10,r8,r9 @(vii)*pu1_ref[ref_main_idx
[all...] |
| /external/v8/test/cctest/ |
| test-disasm-arm.cc | 121 COMPARE(sub(r5, r6, Operand(r10, LSL, 31), LeaveCC, hs),
122 "20465f8a subcs r5, r6, r10, lsl #31");
123 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
124 "30565f0a subccs r5, r6, r10, lsl #30");
125 COMPARE(sub(r5, r6, Operand(r10, LSL, 24), LeaveCC, lo),
126 "30465c0a subcc r5, r6, r10, lsl #24");
127 COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
128 "4056580a submis r5, r6, r10, lsl #16");
161 COMPARE(sbc(r7, r10, Operand(ip), SetCC),
162 "e0da700c sbcs r7, r10, ip")
[all...] |
| /bionic/libc/arch-x86_64/bionic/ |
| syscall.S | 36 * %rcx: arg3 - syscall expects it at %r10
50 mov %r8, %r10
|
| /external/libhevc/decoder/arm/ |
| ihevcd_fmt_conv_420sp_to_420p.s | 102 SUB r10,r7,r8 @// Src Y increment
135 ADD r0, r0, r10
150 SUB r10,r7,r8 @// Src UV increment
190 ADD r1, r1, r10
|
| ihevcd_fmt_conv_420sp_to_420sp.s | 98 SUB r10,r7,r8 @// Src Y increment
139 ADD r0, r0, r10
156 SUB r10,r7,r8 @// Src UV increment
188 ADD r1, r1, r10
|
| /external/libunwind/src/ia64/ |
| ucontext_i.h | 49 #define rTMP r10
|
| /external/libvpx/libvpx/vp8/common/ppc/ |
| sad_altivec.asm | 34 li r10, 16 ;# load offset and loop counter
61 lvx v2, r10, r5
77 lvx v2, r10, r5
95 lvx v2, r10, r5
116 load_aligned_16 v4, r3, r10
117 load_aligned_16 v5, r5, r10
124 load_aligned_16 v6, r3, r10
125 load_aligned_16 v7, r5, r10
|
| copy_altivec.asm | 27 li r10, 16
28 mtctr r10
34 lvx v2, r10, r3
|
| /external/llvm/test/MC/SystemZ/ |
| regs-good.s | 8 #CHECK: lr %r10, %r11 # encoding: [0x18,0xab]
17 lr %r10,%r11
26 #CHECK: lgr %r10, %r11 # encoding: [0xb9,0x04,0x00,0xab]
35 lgr %r10,%r11
44 #CHECK: dlr %r10, %r0 # encoding: [0xb9,0x97,0x00,0xa0]
53 dlr %r10,%r0
113 #CHECK: .cfi_offset %r10, 80
147 .cfi_offset %r10,80
|
| /external/strace/linux/avr32/ |
| userent.h | 7 { uoff(regs.r10), "r10" },
|
| /external/valgrind/coregrind/m_dispatch/ |
| dispatch-amd64-linux.S | 76 pushq %r10
160 popq %r10
217 movq 0(%rcx,%rbx,1), %r10 /* .guest */
219 cmpq %rax, %r10
|
| /frameworks/av/media/libstagefright/codecs/aacenc/src/asm/ARMV5E/ |
| CalcWindowEnergy_v5.s | 33 ldr r10, [r0, #168] @ states0 = blockSwitchingControl->iirStates[0];
66 sub r0, r3, r10 @ accu3 = accu1 - states0;
69 mov r10, r3 @ states0 = accu1;
100 str r10, [r0, #168]
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| syn_filt_neon.s | 59 MOV r10, r13 @ temp = y_buf
62 VLD1.S16 {D4, D5, D6, D7}, [r10]! @ first 16 temp_p
68 ADD r10, r4, r8, LSL #1 @ y[i], yy[i] address
89 STRH r9, [r10] @ yy[i]
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/ppc/ |
| sad_altivec.asm | 34 li r10, 16 ;# load offset and loop counter
61 lvx v2, r10, r5
77 lvx v2, r10, r5
95 lvx v2, r10, r5
116 load_aligned_16 v4, r3, r10
117 load_aligned_16 v5, r5, r10
124 load_aligned_16 v6, r3, r10
125 load_aligned_16 v7, r5, r10
|
| /external/libavc/encoder/arm/ |
| ih264e_evaluate_intra16x16_modes_a9q.s | 100 mov r10, #0
106 movne r10, #1
110 lsl r9, r10, #3
139 add r8, r10, r11
210 vmov.u32 r10, d24[0] @dc
216 moveq r10, r11
224 cmp r8, r10
237 cmp r9, r10
287 str r10 , [r7] @MIN SAD
288 mov r10, #
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| Filt_6k_7k_opt.s | 48 LDR r10, [r3]
49 ADD r10, r3
87 @ not use registers: r4, r10, r12, r14, r5
91 LDR r0, [r10]
106 LDR r0, [r10, #4]
119 LDR r0, [r10, #8]
126 LDR r0, [r10, #12]
133 LDR r0, [r10, #16]
145 LDR r0, [r10, #20]
153 LDR r0, [r10, #24
[all...] |
| /external/compiler-rt/lib/tsan/rtl/ |
| tsan_rtl_amd64.S | 30 push %r10
32 CFI_REL_OFFSET(%r10, 0)
55 pop %r10
79 CFI_RESTORE(%r10)
110 push %r10
112 CFI_REL_OFFSET(%r10, 0)
135 pop %r10
159 CFI_RESTORE(%r10)
|
| /external/libunwind/src/x86_64/ |
| setcontext.S | 55 mov $SIGSET_BYTE_SIZE, %r10
70 movq %rcx,%r10
|
| /external/llvm/test/MC/ARM/ |
| thumb2-cbn-to-next-inst.s | 17 add r10, r11, r12
30 @ CHECK: 16: 0b eb 0c 0a add.w r10, r11, r12
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| omxVCM4P10_TransformDequantChromaDCFromPair_s.S | 31 push {r4-r10, lr}
68 pop {r4-r10, pc}
|
| /external/flac/libFLAC/ppc/as/ |
| lpc_asm.s | 84 li r10,-4
86 lvewx v0,r10,r9
100 add r10,r5,r6
115 cmplw cr0,r5,r10
129 cmplw cr0,r5,r10
143 cmplw cr0,r5,r10
157 cmplw cr0,r5,r10
171 cmplw cr0,r5,r10
185 cmplw cr0,r5,r10
199 cmplw cr0,r5,r10
[all...] |
| /external/flac/libFLAC/ppc/gas/ |
| lpc_asm.s | 86 li r10,-4
88 lvewx v0,r10,r9
102 add r10,r5,r6
117 cmplw cr0,r5,r10
131 cmplw cr0,r5,r10
145 cmplw cr0,r5,r10
159 cmplw cr0,r5,r10
173 cmplw cr0,r5,r10
187 cmplw cr0,r5,r10
201 cmplw cr0,r5,r10
[all...] |
| /external/libvpx/libvpx/vp8/common/arm/armv6/ |
| vp8_variance16x16_armv6.asm | 60 uxtb16 r10, r6, ror #8 ; another two pixels to halfwords
66 smlad r11, r10, r10, r11 ; dual signed multiply, add and accumulate (2)
84 uxtb16 r10, r6, ror #8 ; another two pixels to halfwords
90 smlad r11, r10, r10, r11 ; dual signed multiply, add and accumulate (2)
108 uxtb16 r10, r6, ror #8 ; another two pixels to halfwords
114 smlad r11, r10, r10, r11 ; dual signed multiply, add and accumulate (2)
134 uxtb16 r10, r6, ror #8 ; another two pixels to halfword
[all...] |
| /external/libvpx/libvpx/vp8/encoder/ppc/ |
| rdopt_altivec.asm | 29 li r10, 16
37 lvx v0, r10, r3 ;# Coeff
38 lvx v1, r10, r4 ;# dqcoeff
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/armv6/ |
| vp8_variance16x16_armv6.asm | 60 uxtb16 r10, r6, ror #8 ; another two pixels to halfwords
66 smlad r11, r10, r10, r11 ; dual signed multiply, add and accumulate (2)
84 uxtb16 r10, r6, ror #8 ; another two pixels to halfwords
90 smlad r11, r10, r10, r11 ; dual signed multiply, add and accumulate (2)
108 uxtb16 r10, r6, ror #8 ; another two pixels to halfwords
114 smlad r11, r10, r10, r11 ; dual signed multiply, add and accumulate (2)
134 uxtb16 r10, r6, ror #8 ; another two pixels to halfword
[all...] |
