| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_state_rss.c | 91 EMIT_RS( svga, curr->rt[0].writemask, COLORWRITEENABLE, fail );
|
| svga_tgsi_emit.h | 290 writemask( SVGA3dShaderDestToken dest,
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| svga_tgsi_decl_sm30.c | 193 reg = writemask( dst(emit->ps_true_pos),
|
| /external/mesa3d/src/gallium/tests/graw/ |
| graw_util.h | 166 depthStencilAlpha.depth.writemask = 1;
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_wm_pass2.c | 335 if (inst->writemask & (1<<i)) {
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| brw_disasm.c | 278 char *writemask[16] = { variable
572 err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
601 err |= control (file, "writemask", writemask, inst->bits1.da3src.dest_writemask, NULL);
[all...] |
| brw_wm.h | 144 GLuint writemask:4; member in struct:brw_wm_instruction
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| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_state.c | 586 if (state->depth.writemask) {
617 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT);
635 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT);
642 state->stencil[0].writemask != state->stencil[1].writemask);
[all...] |
| r300_context.c | 460 dsa.depth.writemask = 1;
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| /external/mesa3d/src/gallium/state_trackers/vega/ |
| renderer.c | 746 dsa.depth.writemask = 1;
993 dsa->stencil[0].writemask = 1;
1005 dsa->stencil[0].writemask = ~0;
1115 dsa.stencil[0].writemask = ~0;
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_state.c | 509 S_028430_STENCILWRITEMASK(dsa->writemask[0]));
513 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]));
573 dsa->writemask[0] = state->stencil[0].writemask;
574 dsa->writemask[1] = state->stencil[1].writemask;
577 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
[all...] |
| /external/mesa3d/src/gallium/drivers/r600/ |
| r600_state.c | 811 dsa->writemask[0] = state->stencil[0].writemask;
812 dsa->writemask[1] = state->stencil[1].writemask;
818 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
[all...] |
| r600_pipe.h | 206 ubyte writemask[2]; member in struct:r600_pipe_dsa
305 ubyte writemask[2]; member in struct:r600_stencil_ref
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| evergreen_state.c | 791 dsa->writemask[0] = state->stencil[0].writemask;
792 dsa->writemask[1] = state->stencil[1].writemask;
798 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/ |
| nv50_state.c | 360 SB_DATA (so, cso->depth.writemask);
378 SB_DATA (so, cso->stencil[0].writemask);
394 SB_DATA (so, cso->stencil[1].writemask);
[all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/ |
| nvc0_state.c | 344 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
358 SB_DATA (so, cso->stencil[0].writemask);
372 SB_DATA (so, cso->stencil[1].writemask);
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| /external/mesa3d/src/mesa/main/ |
| ffvertex_prog.c | 546 dst->WriteMask = mask ? mask : WRITEMASK_XYZW;
[all...] |
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_ureg.h | 75 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */
[all...] |
| tgsi_exec.c | 585 uint writemask = inst->Dst[0].Register.WriteMask; local
586 if (writemask == TGSI_WRITEMASK_X ||
587 writemask == TGSI_WRITEMASK_Y ||
588 writemask == TGSI_WRITEMASK_Z ||
589 writemask == TGSI_WRITEMASK_W ||
590 writemask == TGSI_WRITEMASK_NONE) {
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
[all...] |
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_dump_state.c | 484 util_dump_member(stream, bool, &state->depth, writemask);
502 util_dump_member(stream, uint, &state->stencil[i], writemask);
|
| u_blitter.c | 91 void *blend_write_color; /**< blend state with writemask of RGBA */
92 void *blend_keep_color; /**< blend state with writemask of 0 */
185 dsa.depth.writemask = 1;
196 dsa.stencil[0].writemask = 0xff;
201 dsa.depth.writemask = 0;
[all...] |
| /external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d11/ |
| d3d11_screen.h | 520 state.depth.writemask = depth_stencil_state_desc->DepthWriteMask;
534 state.stencil[0].writemask = depth_stencil_state_desc->StencilWriteMask;
541 state.stencil[1].writemask = depth_stencil_state_desc->StencilWriteMask;
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 595 // The writemask for AVX-512 instructions which is contained in EVEX.aaa
596 Reg writemask; member in struct:llvm::X86Disassembler::InternalInstruction
|
| /external/mesa3d/src/gallium/auxiliary/vl/ |
| vl_compositor.c | 461 dsa.depth.writemask = 0;
470 dsa.stencil[i].writemask = 0;
[all...] |
| vl_mpeg12_decoder.c | 781 dsa.depth.writemask = 0;
790 dsa.stencil[i].writemask = 0;
[all...] |
