| /external/llvm/test/CodeGen/Mips/ |
| dagcombine_crash.ll | 8 ; CHECK: sltiu ${{[0-9]*}}, ${{[0-9]*}}, 42
9 ; CHECK: sltiu ${{[0-9]*}}, ${{[0-9]*}}, 23
|
| seteqz.ll | 14 ; 16: sltiu ${{[0-9]+}}, 1
21 ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
|
| setultk.ll | 17 ; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst
|
| seteq.ll | 17 ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
|
| setcc-se.ll | 6 ; CHECK: sltiu ${{[0-9]+}}, $4, 1
92 ; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
125 ; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
|
| octeon.ll | 35 ; MIPS64: sltiu $[[T1:[0-9]+]], $[[T0]], 1
51 ; MIPS64: sltiu $[[T2:[0-9]+]], $[[T1]], 1
|
| cmov.ll | 540 ; sltiu instructions.
546 ; 32-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, 32767
551 ; 32-CMP-DAG: sltiu $[[R0:[0-9]+]], $4, 32767
559 ; 64-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, 32767
564 ; 64-CMP-DAG: sltiu $[[R0:[0-9]+]], $4, 32767
620 ; 32-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, -32768
625 ; 32-CMP-DAG: sltiu $[[R0:[0-9]+]], $4, -32768
633 ; 64-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, -32768
638 ; 64-CMP-DAG: sltiu $[[R0:[0-9]+]], $4, -32768
|
| /external/valgrind/none/tests/mips64/ |
| arithmetic_instruction.c | 14 SLTI, SLTIU, SLTU, SUB,
314 case SLTIU:
317 TEST2("sltiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
318 TEST2("sltiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
319 TEST2("sltiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
320 TEST2("sltiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
321 TEST2("sltiu $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1);
322 TEST2("sltiu $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
323 TEST2("sltiu $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
324 TEST2("sltiu $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1)
[all...] |
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 449 COMPARE(sltiu(a0, a1, 0),
450 "2ca40000 sltiu a0, a1, 0");
451 COMPARE(sltiu(s0, s1, 32767),
452 "2e307fff sltiu s0, s1, 32767");
453 COMPARE(sltiu(t2, t3, -32768),
454 "2d6a8000 sltiu t2, t3, -32768");
455 COMPARE(sltiu(v0, v1, -1),
456 "2c62ffff sltiu v0, v1, -1");
|
| test-disasm-mips64.cc | 602 COMPARE(sltiu(a0, a1, 0),
603 "2ca40000 sltiu a0, a1, 0");
604 COMPARE(sltiu(s0, s1, 32767),
605 "2e307fff sltiu s0, s1, 32767");
606 COMPARE(sltiu(a6, a7, -32768),
607 "2d6a8000 sltiu a6, a7, -32768");
608 COMPARE(sltiu(v0, v1, -1),
609 "2c62ffff sltiu v0, v1, -1");
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| br1.ll | 25 ; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1
|
| icmpa.ll | 26 ; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1
27 ; FIXME: This instruction is redundant. The sltiu can only produce 0 and 1.
|
| /external/llvm/test/MC/Mips/ |
| do_switch1.s | 30 sltiu $1, $2, 4
|
| do_switch2.s | 31 sltiu $1, $3, 4
|
| do_switch3.s | 31 sltiu $4, $1, 4
|
| elf-gprel-32-64.s | 40 sltiu $1, $4, 4
|
| micromips-alu-instructions.s | 23 # CHECK-EL: sltiu $3, $3, 103 # encoding: [0x63,0xb0,0x67,0x00]
60 # CHECK-EB: sltiu $3, $3, 103 # encoding: [0xb0,0x63,0x00,0x67]
95 sltiu $3, $3, 103
|
| /frameworks/native/opengl/libagl/arch-mips/ |
| fixed_asm.S | 45 sltiu $t3,$t1,32 /* t3=1 if t1<32, else t3=0. t1>=32 means the float value is too small. */
|
| /external/llvm/lib/Target/Mips/ |
| MipsCondMov.td | 202 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
207 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
235 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
247 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
254 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
|
| Mips16InstrInfo.td | 439 // op2 can be cmpi or slti/sltiu
663 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
690 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
1078 // Purpose: b = Sltiu rl, imm.
1082 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
1137 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1182 // Format: SLTIU rx, immediate MIPS16e
1187 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
1197 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
1201 // Format: SLTIU rx, immediate MIPS16
[all...] |
| /external/llvm/test/MC/Mips/mips1/ |
| valid.s | 95 sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
97 sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
|
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 121 sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
123 sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
|
| /external/llvm/test/MC/Disassembler/Mips/mips1/ |
| valid-mips1-el.txt | 89 0x55 0xc3 0x39 0x2f # CHECK: sltiu $25, $25, -15531
91 0x55 0xc3 0x38 0x2f # CHECK: sltiu $24, $25, -15531
|
| valid-mips1.txt | 89 0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531
91 0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531
|
| /external/llvm/test/MC/Disassembler/Mips/mips2/ |
| valid-mips2-el.txt | 109 0x55 0xc3 0x39 0x2f # CHECK: sltiu $25, $25, -15531
111 0x55 0xc3 0x38 0x2f # CHECK: sltiu $24, $25, -15531
|
