| /art/test/476-checker-ctor-memory-barrier/ |
| info.txt | 1 Tests if we add memory barriers on constructors when needed (i.e when the
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| /art/runtime/ |
| read_barrier_c.h | 26 // table-lookup read barriers.
46 // A placeholder marker to indicate places to add read barriers in the
48 // after read barriers are added.
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| /external/llvm/test/MC/ARM/ |
| cpu-test.s | 10 // CHECK-ERROR: error: instruction requires: data-barriers
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| thumb-hints.s | 51 @ CHECK-ERROR: error: instruction requires: data-barriers
57 @ CHECK-ERROR: error: instruction requires: data-barriers
63 @ CHECK-ERROR: error: instruction requires: data-barriers
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| /external/valgrind/drd/tests/ |
| pth_barrier_thr_cr.c | 28 int barriers = argc > 1 ? atoi(argv[1]) : 20; local
30 int thread_count = barriers * barrier_participants;
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| /external/regex-re2/util/ |
| atomicops.h | 47 // barriers for the common platforms, as above, but
66 // use read barriers for the readers too.
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| /external/skia/src/core/ |
| SkLazyFnPtr.h | 25 * There is no mutex, and in the fast path, no memory barriers are issued.
52 // No particular memory barriers needed; we're not guarding anything but the pointer itself.
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| /external/llvm/lib/Target/ARM/ |
| ARMOptimizeBarriersPass.cpp | 18 #define DEBUG_TYPE "double barriers"
31 return "optimise barriers pass";
97 /// barriers
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| /external/v8/src/base/ |
| atomicops.h | 18 // versions are provided when no barriers are needed:
68 // This routine implies no memory barriers.
74 // *ptr. This routine implies no memory barriers.
78 // *ptr with the increment applied. This routine implies no memory barriers.
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| atomicops_internals_arm_gcc.h | 19 // Memory barriers on ARM are funky, but the kernel is here to help:
41 // multi-core ARMv6 or ARMv7 device. In this case, memory barriers
248 // But would use 3 barriers per succesful CAS. To save performance,
250 // - A succesful swap uses only 2 barriers (in the kernel helper).
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| atomicops_internals_mips_gcc.h | 22 // This routine implies no memory barriers.
45 // *ptr. This routine implies no memory barriers.
67 // *ptr with the increment applied. This routine implies no memory barriers.
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| atomicops_internals_mips64_gcc.h | 45 // This routine implies no memory barriers.
68 // *ptr. This routine implies no memory barriers.
89 // *ptr with the increment applied. This routine implies no memory barriers.
205 // *ptr. This routine implies no memory barriers.
226 // *ptr with the increment applied. This routine implies no memory barriers.
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| /external/valgrind/helgrind/tests/ |
| bar_trivial.c | 3 barriers. If H fails to notice the pthread_barrier_wait call then
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| /bionic/libc/arch-arm/bionic/ |
| atomics_arm.c | 36 * memory barriers at all.
48 * and now includes full memory barriers to prevent any random memory ordering
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| /external/clang/test/CodeGen/ |
| builtins-arm64.c | 27 void barriers() { function
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| /external/jemalloc/include/jemalloc/internal/ |
| mb.h | 28 * architecture that does not need memory barriers (everything through at least
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| /external/llvm/test/CodeGen/ARM/ |
| 2012-06-12-SchedMemLatency.ll | 5 ; latency regardless of whether they are barriers or not.
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| /external/protobuf/src/google/protobuf/stubs/ |
| atomicops.h | 44 // versions are provided when no barriers are needed:
92 // This routine implies no memory barriers.
98 // *ptr. This routine implies no memory barriers.
102 // *ptr with the increment applied. This routine implies no memory barriers.
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| atomicops_internals_mips_gcc.h | 51 // This routine implies no memory barriers.
74 // *ptr. This routine implies no memory barriers.
95 // *ptr with the increment applied. This routine implies no memory barriers.
206 // *ptr. This routine implies no memory barriers.
227 // *ptr with the increment applied. This routine implies no memory barriers.
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| /external/skia/include/ports/ |
| SkAtomics_sync.h | 27 // These barriers only support our majority use cases: acquire and relaxed loads, release stores.
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| /external/webrtc/src/system_wrappers/interface/ |
| atomic32.h | 14 // Note: uses full memory barriers.
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| /ndk/docs/Programmers_Guide/html/ |
| md_4__additional__info__a_n_d_r_o_i_d-_a_t_o_m_i_c_s.html | 69 <p>The main issue is that the implementation of these functions, as provided by the C library, did not provide any associated memory barriers. This is by design, because the platform code that uses them does insert explicit barriers around these operations.</p>
70 <p>The functions were only exposed through the NDK by mistake, they were not supposed to be used from applications. Any application code that use them without inserting its own barriers may experiment incorrect behaviour, which can result in bugs that are very hard to reproduce and diagnose.</p>
72 <p>The problem is only likely to be seen on devices running Android 3.0 to Android 4.1. The C library implementation in 4.1 has been updated to provide full memory barriers as well. This ensures existing native code keeps working correctly on this platform and future ones, even if they were not recompiled.</p>
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| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/sysroot/usr/include/linux/ |
| virtio_blk.h | 10 #define VIRTIO_BLK_F_BARRIER 0 /* Does host support barriers? */
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| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| alias.h | 48 memory barriers, including an address of SCRATCH. */
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| /external/jsilver/src/com/google/clearsilver/jsilver/syntax/ |
| DataCommandConsolidator.java | 115 // var, lvar, evar, uvar, name: all unconditional barriers.
142 // loop, each: block barriers.
241 // include, hard include, linclude, hard linclude unconditional barriers.
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