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    Searched full:buffer_store_dword (Results 1 - 25 of 78) sorted by null

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/external/llvm/test/CodeGen/R600/
reorder-stores.ll	58 ; SI: buffer_store_dword 59 ; SI: buffer_store_dword 60 ; SI: buffer_store_dword 61 ; SI: buffer_store_dword 63 ; SI: buffer_store_dword 64 ; SI: buffer_store_dword 65 ; SI: buffer_store_dword 66 ; SI: buffer_store_dword 68 ; SI: buffer_store_dword 69 ; SI: buffer_store_dword     [all...]
copy-illegal-type.ll	6 ; SI: buffer_store_dword [[REG]] 16 ; SI: buffer_store_dword [[REG]] 17 ; SI: buffer_store_dword [[REG]] 28 ; SI: buffer_store_dword [[REG]] 29 ; SI: buffer_store_dword [[REG]] 30 ; SI: buffer_store_dword [[REG]] 42 ; SI: buffer_store_dword [[REG]] 43 ; SI: buffer_store_dword [[REG]] 44 ; SI: buffer_store_dword [[REG]] 45 ; SI: buffer_store_dword [[REG]     [all...]
work-item-intrinsics.ll	12 ; GCN: buffer_store_dword [[VVAL]] 27 ; GCN: buffer_store_dword [[VVAL]] 42 ; GCN: buffer_store_dword [[VVAL]] 57 ; GCN: buffer_store_dword [[VVAL]] 72 ; GCN: buffer_store_dword [[VVAL]] 87 ; GCN: buffer_store_dword [[VVAL]] 102 ; GCN: buffer_store_dword [[VVAL]] 117 ; GCN: buffer_store_dword [[VVAL]] 132 ; GCN: buffer_store_dword [[VVAL]] 147 ; GCN: buffer_store_dword [[VVAL]     [all...]
missing-store.ll	10 ; SI: buffer_store_dword 12 ; SI: buffer_store_dword
llvm.AMDGPU.clamp.ll	12 ; SI: buffer_store_dword [[RESULT]] 25 ; SI: buffer_store_dword [[RESULT]] 37 ; SI: buffer_store_dword [[RESULT]] 49 ; SI: buffer_store_dword [[RESULT]] 62 ; SI: buffer_store_dword [[RESULT]]
hsa.ll	8 ; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0
infinite-loop.ll	7 ; SI: buffer_store_dword [[REG]]
llvm.AMDGPU.brev.ll	10 ; SI: buffer_store_dword [[VRESULT]], 21 ; SI: buffer_store_dword [[RESULT]],
llvm.AMDGPU.flbit.i32.ll	10 ; SI: buffer_store_dword [[VRESULT]], 21 ; SI: buffer_store_dword [[RESULT]],
use-sgpr-multiple-times.ll	12 ; GCN: buffer_store_dword [[RESULT]] 22 ; GCN: buffer_store_dword [[RESULT]] 36 ; GCN: buffer_store_dword [[RESULT]] 50 ; GCN: buffer_store_dword [[RESULT]] 64 ; GCN: buffer_store_dword [[RESULT]] 74 ; GCN: buffer_store_dword [[RESULT]] 84 ; GCN: buffer_store_dword [[RESULT]] 95 ; GCN: buffer_store_dword [[RESULT]]
shl_add_constant.ll	10 ; SI: buffer_store_dword [[RESULT]] 25 ; SI-DAG: buffer_store_dword [[ADDREG]] 26 ; SI-DAG: buffer_store_dword [[SHLREG]] 44 ; SI: buffer_store_dword [[RESULT]] 63 ; SI: buffer_store_dword [[VRESULT]] 79 ; SI: buffer_store_dword [[VRESULT]]
imm.ll	39 ; CHECK-NEXT: buffer_store_dword [[REG]] 47 ; CHECK: buffer_store_dword [[REG]] 55 ; CHECK: buffer_store_dword [[REG]] 63 ; CHECK: buffer_store_dword [[REG]] 71 ; CHECK: buffer_store_dword [[REG]] 79 ; CHECK: buffer_store_dword [[REG]] 87 ; CHECK: buffer_store_dword [[REG]] 95 ; CHECK: buffer_store_dword [[REG]] 103 ; CHECK: buffer_store_dword [[REG]] 111 ; CHECK: buffer_store_dword [[REG]     [all...]
cvt_f32_ubyte.ll	9 ; SI: buffer_store_dword [[CONV]], 140 ; SI: buffer_store_dword 141 ; SI: buffer_store_dword 142 ; SI: buffer_store_dword 143 ; SI: buffer_store_dword 144 ; SI: buffer_store_dword 145 ; SI: buffer_store_dword 146 ; SI: buffer_store_dword 147 ; SI: buffer_store_dword 159 ; SI: buffer_store_dword [[CONV]]     [all...]
global_atomics.ll	14 ; SI: buffer_store_dword [[RET]] 35 ; SI: buffer_store_dword [[RET]] 55 ; SI: buffer_store_dword [[RET]] 74 ; SI: buffer_store_dword [[RET]] 94 ; SI: buffer_store_dword [[RET]] 115 ; SI: buffer_store_dword [[RET]] 135 ; SI: buffer_store_dword [[RET]] 154 ; SI: buffer_store_dword [[RET]] 174 ; SI: buffer_store_dword [[RET]] 195 ; SI: buffer_store_dword [[RET]     [all...]
llvm.AMDGPU.bfe.i32.ll	89 ; SI: buffer_store_dword [[VREG]], 184 ; SI: buffer_store_dword [[VREG]], 196 ; SI: buffer_store_dword [[VREG]], 208 ; SI: buffer_store_dword [[VREG]], 220 ; SI: buffer_store_dword [[VREG]], 232 ; SI: buffer_store_dword [[VREG]], 244 ; SI: buffer_store_dword [[VREG]], 256 ; SI: buffer_store_dword [[VREG]], 268 ; SI: buffer_store_dword [[VREG]], 280 ; SI: buffer_store_dword [[VREG]]     [all...]
llvm.AMDGPU.bfe.u32.ll	196 ; SI: buffer_store_dword [[VREG]], 332 ; SI: buffer_store_dword [[VREG]], 344 ; SI: buffer_store_dword [[VREG]], 356 ; SI: buffer_store_dword [[VREG]], 368 ; SI: buffer_store_dword [[VREG]], 380 ; SI: buffer_store_dword [[VREG]], 392 ; SI: buffer_store_dword [[VREG]], 404 ; SI: buffer_store_dword [[VREG]], 416 ; SI: buffer_store_dword [[VREG]], 428 ; SI: buffer_store_dword [[VREG]]     [all...]
si-triv-disjoint-mem-access.ll	15 ; CI: buffer_store_dword 34 ; CI: buffer_store_dword 55 ; CI: buffer_store_dword 78 ; CI: buffer_store_dword 80 ; CI: buffer_store_dword 101 ; CI: buffer_store_dword 123 ; CI: buffer_store_dword 142 ; CI: buffer_store_dword 163 ; CI: buffer_store_dword 184 ; CI: buffer_store_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:1     [all...]
fmax3.ll	11 ; SI: buffer_store_dword [[RESULT]], 29 ; SI: buffer_store_dword [[RESULT]],
fmin3.ll	12 ; SI: buffer_store_dword [[RESULT]], 30 ; SI: buffer_store_dword [[RESULT]],
schedule-global-loads.ll	14 ; SI: buffer_store_dword [[REG0]] 15 ; SI: buffer_store_dword [[REG1]]
ctpop.ll	15 ; GCN: buffer_store_dword [[VRESULT]], 29 ; GCN: buffer_store_dword [[RESULT]], 46 ; GCN: buffer_store_dword [[RESULT]], 65 ; GCN-NEXT: buffer_store_dword [[RESULT]], 178 ; GCN: buffer_store_dword [[RESULT]], 193 ; GCN: buffer_store_dword [[RESULT]], 210 ; GCN: buffer_store_dword [[RESULT]], 224 ; GCN: buffer_store_dword [[RESULT]], 240 ; GCN: buffer_store_dword [[RESULT]], 257 ; GCN: buffer_store_dword [[RESULT]]     [all...]
llvm.AMDGPU.barrier.global.ll	6 ; SI: buffer_store_dword
llvm.AMDGPU.barrier.local.ll	7 ; SI: buffer_store_dword
llvm.AMDGPU.fract.ll	16 ; GCN: buffer_store_dword [[RESULT]] 29 ; GCN: buffer_store_dword [[RESULT]] 42 ; GCN: buffer_store_dword [[RESULT]] 56 ; GCN: buffer_store_dword [[RESULT]]
/external/llvm/test/MC/R600/
mubuf.s	152 buffer_store_dword v1, s[4:7], s1 label 153 // CHECK: buffer_store_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x70,0xe0,0x00,0x01,0x01,0x01] 155 buffer_store_dword v1, s[4:7], s1 offset:4 label 156 // CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x01,0x01] 158 buffer_store_dword v1, s[4:7], s1 offset:4 glc label 159 // CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0x01,0x01] 161 buffer_store_dword v1, s[4:7], s1 offset:4 slc label 162 // CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x41,0x01] 164 buffer_store_dword v1, s[4:7], s1 offset:4 tfe label 165 // CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x81,0x01 167 buffer_store_dword v1, s[4:7], s1 tfe glc label 170 buffer_store_dword v1, s[4:7], s1 offset:4 glc tfe slc label 173 buffer_store_dword v1, s[4:7], s1 glc tfe slc offset:4 label 180 buffer_store_dword v1, v2, s[4:7], s1 offen label 183 buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 label 186 buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc label 189 buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc label 192 buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 tfe label 195 buffer_store_dword v1, v2, s[4:7], s1 offen tfe glc label 198 buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc tfe slc label 201 buffer_store_dword v1, v2, s[4:7], s1 offen glc tfe slc offset:4 label 208 buffer_store_dword v1, v2, s[4:7], s1 idxen label 211 buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 label 214 buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc label 217 buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc label 220 buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 tfe label 223 buffer_store_dword v1, v2, s[4:7], s1 idxen tfe glc label 226 buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc tfe slc label 229 buffer_store_dword v1, v2, s[4:7], s1 idxen glc tfe slc offset:4 label 236 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen label 239 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 label 242 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc label 245 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc label 248 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe label 251 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen tfe glc label 254 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc tfe slc label 257 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe slc offset:4 label 264 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 label 267 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 label 270 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc label 273 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc label 276 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe label 279 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 tfe glc label 282 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc tfe slc label 285 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe slc offset:4 label 343 buffer_store_dword v1 s[4:7], s1 label     [all...]

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