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  /external/llvm/test/CodeGen/X86/
fast-isel-sse12-fptoint.ll 6 ; SSE: cvttss2si %xmm0, %eax
13 %5 = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %4)
16 declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone
20 ; SSE: cvttss2si %xmm0, %rax
vec_ss_load_fold.ll 15 %tmp.upgrd.1 = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 ) ; <i32> [#uses=1]
30 %tmp = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 ) ; <i32> [#uses=1]
47 declare i32 @llvm.x86.sse.cvttss2si(<4 x float>)
half.ll 79 ; CHECK-LIBCALL-NEXT: cvttss2si %xmm0, %rax
124 ; CHECK-LIBCALL-NEXT: cvttss2si [[REG2]], [[REG3:%[a-z0-9]+]]
127 ; CHECK-LIBCALL-NEXT: cvttss2si %xmm0, [[REG5:%[a-z0-9]+]]
sse-intrinsics-x86.ll 104 ; CHECK: cvttss2si
105 %res = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0) ; <i32> [#uses=1]
108 declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone
stack-folding-fp-sse42.ll 488 ;CHECK: cvttss2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
496 ;CHECK: cvttss2si {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 16-byte Folded Reload
498 %2 = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0)
501 declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone
505 ;CHECK: cvttss2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 4-byte Folded Reload
513 ;CHECK: cvttss2si {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 16-byte Folded Reload
    [all...]
  /external/llvm/test/Transforms/ConstProp/
calls.ll 37 %i1 = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> <float 1.75, float undef, float undef, float undef>) nounwind
56 declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone
  /external/v8/test/cctest/
test-disasm-x64.cc 354 __ cvttss2si(rdx, Operand(rbx, rcx, times_4, 10000));
355 __ cvttss2si(rdx, xmm1);
test-assembler-ia32.cc 166 __ cvttss2si(eax, Operand(esp, 4));
173 // don't print the code - our disassembler can't handle cvttss2si
580 __ cvttss2si(eax, xmm2);
test-disasm-ia32.cc 406 __ cvttss2si(edx, Operand(ebx, ecx, times_4, 10000));
test-assembler-x64.cc 721 __ cvttss2si(rax, xmm2);
  /external/valgrind/memcheck/tests/amd64/
sse_memory.c 206 //TEST_INSN( &AllMask, 0,cvttss2si)
437 //TEST_INSN( &AllMask, 0,cvttss2si)
  /art/compiler/utils/x86_64/
assembler_x86_64_test.cc     [all...]
assembler_x86_64.h 409 void cvttss2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
410 void cvttss2si(CpuRegister dst, XmmRegister src, bool is64bit);
assembler_x86_64.cc 755 void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src) { function in class:art::x86_64::X86_64Assembler
756 cvttss2si(dst, src, false);
760 void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src, bool is64bit) { function in class:art::x86_64::X86_64Assembler
    [all...]
  /external/valgrind/none/tests/amd64/
insn_sse.def 57 cvttss2si xmm.ps[12.34,56.78,43.21,87.65] r32.sd[99] => 1.sd[12]
58 cvttss2si m128.ps[56.78,12.34,87.65,43.21] r32.sd[99] => 1.sd[56]
  /external/valgrind/none/tests/x86/
insn_sse.def 57 cvttss2si xmm.ps[12.34,56.78,43.21,87.65] r32.sd[99] => 1.sd[12]
58 cvttss2si m128.ps[56.78,12.34,87.65,43.21] r32.sd[99] => 1.sd[56]
  /external/v8/src/ia32/
assembler-ia32.h 941 void cvttss2si(Register dst, const Operand& src);
942 void cvttss2si(Register dst, XMMRegister src) {
943 cvttss2si(dst, Operand(src));
    [all...]
  /external/llvm/test/Transforms/InstCombine/
vec_demanded_elts.ll 20 %tmp.upgrd.1 = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 ) ; <i32> [#uses=1]
59 %tmp2 = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> %v23)
134 declare i32 @llvm.x86.sse.cvttss2si(<4 x float>)
  /art/compiler/utils/x86/
assembler_x86.h 305 void cvttss2si(Register dst, XmmRegister src);
  /external/llvm/lib/Target/X86/
X86InstrSSE.td     [all...]
  /external/v8/src/x64/
assembler-x64.h     [all...]
disasm-x64.cc     [all...]
  /external/llvm/test/MC/X86/
x86-32-coverage.s     [all...]
  /external/elfutils/src/tests/
testfile44.expect.bz2 
  /art/compiler/optimizing/
intrinsics_x86_64.cc 742 __ cvttss2si(out, inPlusPointFive);
    [all...]

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