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    Searched full:ds_read2st64_b32 (Results 1 - 7 of 7) sorted by null

  /external/llvm/test/CodeGen/R600/
ds_read2_offset_order.ll 11 ; SI: ds_read2st64_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:0 offset1:4
ds_read2st64.ll 8 ; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1
27 ; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2
47 ; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:255
67 ; SI-NOT: ds_read2st64_b32
87 ; SI-NOT: ds_read2st64_b32
103 ; SI-NOT: ds_read2st64_b32
shl_add_ptr.ll 74 ; SI-NEXT: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9
  /external/llvm/test/MC/R600/
ds.s 186 ds_read2st64_b32 v[8:9], v2 label
187 // CHECK: ds_read2st64_b32 v[8:9], v2 ; encoding: [0x00,0x00,0xe0,0xd8,0x02,0x00,0x00,0x08]
  /external/llvm/lib/Target/R600/
SILoadStoreOptimizer.cpp 237 Opc = (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64;
SIInstructions.td     [all...]
SIInstrInfo.cpp 179 case AMDGPU::DS_READ2ST64_B32:
    [all...]

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