| /external/llvm/test/MC/X86/AlignedBundling/ |
| different-sections.s | 11 imull $17, %ebx, %ebp
12 imull $17, %ebx, %ebp
14 imull $17, %ebx, %ebp
16 # CHECK-NEXT: 8: imull
20 imull $17, %ebx, %ebp
21 imull $17, %ebx, %ebp
23 imull $17, %ebx, %ebp
25 # CHECK-NEXT: 8: imull
|
| switch-section-locked-error.s | 10 imull $17, %ebx, %ebp
12 imull $17, %ebx, %ebp
15 imull $17, %ebx, %ebp
|
| align-mode-argument-error.s | 7 imull $17, %ebx, %ebp
|
| bundle-lock-option-error.s | 8 imull $17, %ebx, %ebp
|
| lock-without-bundle-mode-error.s | 7 imull $17, %ebx, %ebp
|
| unlock-without-lock-error.s | 8 imull $17, %ebx, %ebp
|
| single-inst-bundling.s | 20 imull $17, %ebx, %ebp
21 # This imull is 3 bytes long and should have started at 0xe, so two bytes
24 # CHECK-NEXT: 10: imull
43 imull %ebx, %eax
|
| relax-in-bundle-group.s | 17 imull $17, %ebx, %ebp
40 imull %ebx, %eax
|
| /external/llvm/test/CodeGen/X86/ |
| atom-sched.ll | 14 ; atom: imull
16 ; atom: imull
17 ; slm: imull
19 ; slm: imull
20 ; CHECK: imull
22 ; CHECK: imull
|
| sdiv-exact.ll | 7 ; CHECK: imull $-1030792151, 4(%esp)
16 ; CHECK-NEXT: imull $-1431655765
|
| subreg-to-reg-3.ll | 3 ; CHECK: imull
|
| divide-by-constant.ll | 10 ; CHECK: imull $63551, %eax
21 ; CHECK: imull $43691, %eax
33 ; CHECK-NEXT: imull $171, %eax
44 ; CHECK: imull $1986, %eax
60 ; CHECK: imull $26215, %eax
83 ; CHECK: imull $211
93 ; CHECK: imull $71
|
| misched-matrix.ll | 20 ; TOPDOWN: imull {{[0-9]*}}(
22 ; TOPDOWN: imull {{[0-9]*}}(
28 ; scheduled independently, and that the imull/adds are interleaved.
32 ; ILPMIN: imull
33 ; ILPMIN: imull
35 ; ILPMIN: imull
37 ; ILPMIN: imull
40 ; ILPMIN: imull
41 ; ILPMIN: imull
43 ; ILPMIN: imull
[all...] |
| misched-balance.ll | 12 ; imull folded loads should be in order and interleaved with addl, never
20 ; CHECK: imull 4
21 ; CHECK-NOT: {{imull|rsp}}
23 ; CHECK: imull 8
24 ; CHECK-NOT: {{imull|rsp}}
26 ; CHECK: imull 12
27 ; CHECK-NOT: {{imull|rsp}}
29 ; CHECK: imull 16
30 ; CHECK-NOT: {{imull|rsp}}
32 ; CHECK: imull 2
[all...] |
| memset-2.ll | 28 ; CHECK: imull $16843009
36 ; CHECK: imull $16843009
|
| 2010-09-01-RemoveCopyByCommutingDef.ll | 13 ; The imull clobbers a 32-bit register.
14 ; CHECK: imull %{{...}}, %e[[CLOBBER:..]]
|
| sink-blockfreq.ll | 13 ; MSINK_BFI-NEXT: imull
16 ; MSINK_NOBFI: imull
|
| imul.ll | 73 ; X86: imull
83 ; X86-NEXT: imull
|
| smul-with-overflow.ll | 21 ; CHECK: imull
40 ; CHECK: imull
|
| vector-idiv.ll | 284 ; SSE41-NEXT: imull $-109, %eax, %ecx
294 ; SSE41-NEXT: imull $-109, %ecx, %edx
306 ; SSE41-NEXT: imull $-109, %eax, %ecx
317 ; SSE41-NEXT: imull $-109, %eax, %ecx
328 ; SSE41-NEXT: imull $-109, %eax, %ecx
339 ; SSE41-NEXT: imull $-109, %eax, %ecx
350 ; SSE41-NEXT: imull $-109, %eax, %ecx
361 ; SSE41-NEXT: imull $-109, %eax, %ecx
372 ; SSE41-NEXT: imull $-109, %eax, %ecx
383 ; SSE41-NEXT: imull $-109, %eax, %ec
[all...] |
| machine-cse.ll | 56 ; CHECK: imull
64 ; CHECK-NOT: imull
|
| /external/compiler-rt/lib/builtins/i386/ |
| muldi3.S | 16 imull %eax, %ecx // b.lo * a.hi
20 imull %edx, %ebx // a.lo * b.hi
|
| udivdi3.S | 59 imull %edi, %eax // q*bhi
91 imull %edi, %eax // q*bhi
|
| umoddi3.S | 60 imull %edi, %eax // q*bhi
96 imull %edi, %eax // q*bhi
|
| /external/llvm/test/Instrumentation/AddressSanitizer/X86/ |
| bug_11395.ll | 63 %2 = call { i32*, i32*, i32* } asm sideeffect "1: \0A\09xor %esi, %esi\0A\09xor %ecx, %ecx\0A\09jmp *$5 \0A\09ff_mlp_firorder_8: \0A\09mov 0x1c+0($0), %eax\0A\09imull 0x1c+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_7: \0A\09mov 0x18+0($0), %eax\0A\09imull 0x18+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_6: \0A\09mov 0x14+0($0), %eax\0A\09imull 0x14+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_5: \0A\09mov 0x10+0($0), %eax\0A\09imull 0x10+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_4: \0A\09mov 0x0c+0($0), %eax\0A\09imull 0x0c+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_3: \0A\09mov 0x08+0($0), %eax\0A\09imull 0x08+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_2: \0A\09mov 0x04+0($0), %eax\0A\09imull 0x04+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_1: \0A\09mov 0x00+0($0), %eax\0A\09imull 0x00+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_0:\0A\09jmp *$6 \0A\09ff_mlp_iirorder_4: \0A\09mov 0x0c+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x0c+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_3: \0A\09mov 0x08+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x08+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09 (…)
[all...] |
