| /external/valgrind/none/tests/mips32/ |
| unaligned_load_store.c | 46 printMem("PRE lwr");
49 "lwr $t0, 4($a0)" "\n\t"
52 "lwr $t1, 5($a0)" "\n\t"
55 "lwr $t2, 6($a0)" "\n\t"
58 "lwr $t3, 7($a0)" "\n\t"
64 printMem("POST lwr");
|
| unaligned_load_store.stdout.exp-BE | 17 PRE lwr
25 POST lwr
|
| unaligned_load_store.stdout.exp-LE | 17 PRE lwr
25 POST lwr
|
| /external/valgrind/none/tests/mips64/ |
| unaligned_load_store.c | 46 printMem("PRE lwr");
49 "lwr $t0, 4($a0)" "\n\t"
52 "lwr $t1, 5($a0)" "\n\t"
55 "lwr $t2, 6($a0)" "\n\t"
58 "lwr $t3, 7($a0)" "\n\t"
64 printMem("POST lwr");
|
| unaligned_load_store.stdout.exp-BE | 17 PRE lwr
25 POST lwr
|
| unaligned_load_store.stdout.exp-LE | 17 PRE lwr
25 POST lwr
|
| load_store.c | 76 /* lwr */
78 TEST1("lwr", i, reg_val1);
81 TEST1("lwr", i, reg_val2);
|
| /external/clang/test/CodeGen/ |
| mips-constraints-mem.c | 11 // switched due to the lwl/lwr instruction pairs.
12 // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R,~{$1}"(i32* %{{[0-9,a-f]+}}) #1,
21 "lwr %0, 2 + %1\n\t"
|
| /external/llvm/test/MC/Mips/ |
| sym-offset.ll | 12 ; check that the immediate fields of lwl and lwr are three apart.
14 ; 9841000b lwr at,11(v0)
|
| micromips-loadstore-unaligned.s | 13 # CHECK-EL: lwr $4, 16($5) # encoding: [0x85,0x60,0x10,0x10]
20 # CHECK-EB: lwr $4, 16($5) # encoding: [0x60,0x85,0x10,0x10]
24 lwr $4, 16($5)
|
| /external/v8/src/mips/ |
| codegen-mips.cc | 138 __ lwr(t8, MemOperand(a1));
300 __ lwr(v1, MemOperand(a1));
308 __ lwr(v1,
343 __ lwr(t0, MemOperand(a1));
344 __ lwr(t1, MemOperand(a1, 1, loadstore_chunk));
345 __ lwr(t2, MemOperand(a1, 2, loadstore_chunk));
351 __ lwr(t3, MemOperand(a1, 3, loadstore_chunk)); // Maybe in delay slot.
357 __ lwr(t4, MemOperand(a1, 4, loadstore_chunk));
358 __ lwr(t5, MemOperand(a1, 5, loadstore_chunk));
359 __ lwr(t6, MemOperand(a1, 6, loadstore_chunk))
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| load-store-left-right.ll | 29 ; MIPS32-EL: lwr $[[R0]], 0($[[R1]])
32 ; MIPS32-EB: lwr $[[R0]], 3($[[R1]])
38 ; MIPS64-EL: lwr $[[R0]], 0($[[R1]])
41 ; MIPS64-EB: lwr $[[R0]], 3($[[R1]])
81 ; MIPS32-EL: lwr $2, 0($[[R1]])
83 ; MIPS32-EL: lwr $3, 4($[[R1]])
86 ; MIPS32-EB: lwr $2, 3($[[R1]])
88 ; MIPS32-EB: lwr $3, 7($[[R1]])
112 ; MIPS32-EL: lwr $[[R0]], 0($[[R1]])
115 ; MIPS32-EB: lwr $[[R0]], 3($[[R1]]
[all...] |
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| row_mips.cc | 40 "lwr $t8, 0(%[src]) \n"
198 "lwr $v1, 0(%[src]) \n"
231 "lwr $t0, 0(%[src]) \n"
233 "lwr $t1, 4(%[src]) \n"
239 "lwr $t2, 8(%[src]) \n"
241 "lwr $t3, 12(%[src]) \n"
243 "lwr $t4, 16(%[src]) \n"
245 "lwr $t5, 20(%[src]) \n"
247 "lwr $t6, 24(%[src]) \n"
249 "lwr $t7, 28(%[src]) \n
[all...] |
| /external/v8/src/mips64/ |
| codegen-mips64.cc | 144 __ lwr(t8, MemOperand(a1));
300 __ lwr(v1, MemOperand(a1));
334 __ lwr(a4, MemOperand(a1));
335 __ lwr(a5, MemOperand(a1, 1, loadstore_chunk));
336 __ lwr(a6, MemOperand(a1, 2, loadstore_chunk));
342 __ lwr(a7, MemOperand(a1, 3, loadstore_chunk)); // Maybe in delay slot.
348 __ lwr(t0, MemOperand(a1, 4, loadstore_chunk));
349 __ lwr(t1, MemOperand(a1, 5, loadstore_chunk));
350 __ lwr(t2, MemOperand(a1, 6, loadstore_chunk));
351 __ lwr(t3, MemOperand(a1, 7, loadstore_chunk))
[all...] |
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips1-wrong-error.s | 11 lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips1-wrong-error.s | 11 lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips3-wrong-error.s | 17 lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /bionic/libc/arch-mips/include/machine/ |
| asm.h | 64 #define LWHI lwr
73 #define LWLO lwr
|
| /development/ndk/platforms/android-21/arch-mips/include/machine/ |
| asm.h | 66 #define LWHI lwr
75 #define LWLO lwr
|
| /development/ndk/platforms/android-21/arch-mips64/include/machine/ |
| asm.h | 66 #define LWHI lwr
75 #define LWLO lwr
|
| /development/ndk/platforms/android-9/arch-mips/include/machine/ |
| asm.h | 69 #define LWHI lwr
78 #define LWLO lwr
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/machine/ |
| asm.h | 69 #define LWHI lwr
78 #define LWLO lwr
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/machine/ |
| asm.h | 69 #define LWHI lwr
78 #define LWLO lwr
|
| /prebuilts/ndk/9/platforms/android-12/arch-mips/usr/include/machine/ |
| asm.h | 69 #define LWHI lwr
78 #define LWLO lwr
|
| /prebuilts/ndk/9/platforms/android-13/arch-mips/usr/include/machine/ |
| asm.h | 69 #define LWHI lwr
78 #define LWLO lwr
|
