/external/llvm/test/Analysis/CostModel/X86/ |
masked-intrinsic-cost.ll | 5 ; AVX2: Found an estimated cost of 4 {{.*}}.masked 8 %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst) 13 ; AVX2: Found an estimated cost of 4 {{.*}}.masked 16 %res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst) 21 ; AVX2: Found an estimated cost of 4 {{.*}}.masked 24 call void @llvm.masked.store.v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask) 29 ; AVX2: Found an estimated cost of 4 {{.*}}.masked 32 %res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 4, <8 x i1>%mask, <8 x float>%dst) 37 ; AVX2: Found an estimated cost of 5 {{.*}}.masked 40 call void @llvm.masked.store.v2f32(<2 x float>%val, <2 x float>* %addr, i32 4, <2 x i1>%mask [all...] |
/external/llvm/test/CodeGen/X86/ |
2009-11-13-VirtRegRewriterBug.ll | 9 %mask133.masked.masked.masked.masked.masked.masked = or i640 undef, undef ; <i640> [#uses=1] 31 %mask271.masked.masked.masked.masked.masked.masked.masked = or i256 0, undef ; <i256> [#uses=2 [all...] |
masked_memop.ll | 15 ; AVX_SCALAR-NOT: masked 22 %res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>undef) 35 %res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>zeroinitializer) 43 ; AVX_SCALAR-NOT: masked 52 call void @llvm.masked.store.v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%mask) 65 %res = call <16 x float> @llvm.masked.load.v16f32(<16 x float>* %addr, i32 4, <16 x i1>%mask, <16 x float> %dst) 79 %res = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %addr, i32 4, <8 x i1>%mask, <8 x double>%dst) 91 %res = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst) 103 %res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1>%mask, <4 x float>%dst) 115 %res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst [all...] |
narrow-shl-load.ll | 19 %shl15.masked = and i64 %shl15, 4294967294 20 %and17 = or i64 %shl15.masked, %conv11
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/external/llvm/test/CodeGen/R600/ |
llvm.exp2.ll | 8 ;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 9 ;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 10 ;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 26 ;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 27 ;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 28 ;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 29 ;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 30 ;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 31 ;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 51 ;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) [all...] |
llvm.log2.ll | 8 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 9 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 10 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 26 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 27 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 28 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 29 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 30 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 31 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) 51 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED) [all...] |
input-mods.ll | 8 ;CM: EXP_IEEE T{{[0-9]+}}.Y (MASKED), -|T{{[0-9]+}}.X| 9 ;CM: EXP_IEEE T{{[0-9]+}}.Z (MASKED), -|T{{[0-9]+}}.X| 10 ;CM: EXP_IEEE * T{{[0-9]+}}.W (MASKED), -|T{{[0-9]+}}.X|
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literals.ll | 52 ; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0 53 ; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0 54 ; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0
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trunc.ll | 75 ; SI: v_and_b32_e64 [[MASKED:v[0-9]+]], 1, s[[SLO]] 76 ; SI: v_cmp_eq_i32_e32 vcc, 1, [[MASKED]] 87 ; SI: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]] 88 ; SI: v_cmp_eq_i32_e32 vcc, 1, [[MASKED]]
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/external/llvm/test/CodeGen/PowerPC/ |
rlwimi-dyn-and.ll | 17 %shl161.masked = and i32 %shl161, %const_mat 18 %conv174 = or i32 %shl170, %shl161.masked 37 %shl161.masked = and i32 %shl161, 32768 38 %conv174 = or i32 %shl170, %shl161.masked
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rlwinm2.ll | 25 %tmp2.masked = and i32 %tmp2, 96 ; <i32> [#uses=1] 26 %tmp5 = or i32 %tmp1, %tmp2.masked ; <i32> [#uses=1]
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/external/llvm/test/Transforms/ConstantHoisting/PowerPC/ |
masks.ll | 25 %shl161.masked = and i32 %shl161, 32768 26 %conv174 = or i32 %shl170, %shl161.masked 55 %shl161.masked = and i32 %shl161, 32773 56 %conv174 = or i32 %shl170, %shl161.masked
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/external/skia/src/opts/ |
SkBlitRow_opts_arm.cpp | 139 "and r9, ip, r7 \n\t" /* r9 = br masked by ip */ 141 "and r10, ip, r7, lsr #8 \n\t" /* r10 = ag masked by ip */ 155 "and r9, ip, r8 \n\t" /* r9 = br masked by ip */ 157 "and r10, ip, r8, lsr #8 \n\t" /* r10 = ag masked by ip */ 183 "and r9, ip, r7 \n\t" /* r9 = br masked by ip */ 186 "and r10, ip, r7, lsr #8 \n\t" /* r10 = ag masked by ip */ 249 "and r11, r12, r5, lsr #8 \n\t" /* ag = r11 = r5 masked by r12 lsr by #8 */ 250 "and r4, r12, r5 \n\t" /* rb = r4 = r5 masked by r12 */ 253 "and r11, r11, r12, lsl #8 \n\t" /* ag masked by reverse mask (r12) */ 254 "and r4, r12, r4, lsr #8 \n\t" /* rb masked by mask (r12) * [all...] |
/external/valgrind/gdbserver_tests/ |
nlsigvgdb.vgtest | 4 # But if this signal is masked, then vgdb does not recuperate the control
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/external/mesa3d/src/gallium/drivers/radeon/ |
R600ExpandSpecialInstrs.cpp | 76 // TO_Y (write masked) = DP4 T1_Y, T2_Y 77 // TO_Z (write masked) = DP4 T1_Z, T2_Z 78 // TO_W (write masked) = DP4 T1_W, T2_W 84 // T0_Y (write masked) = MULLO_INT T1_X, T2_X 85 // T0_Z (write masked) = MULLO_INT T1_X, T2_X 86 // T0_W (write masked) = MULLO_INT T1_X, T2_X
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/external/llvm/test/Transforms/LoopVectorize/X86/ |
masked_load_store.ll | 5 ;AVX1-NOT: llvm.masked 23 ;AVX2: call <8 x i32> @llvm.masked.load.v8i32 25 ;AVX2: call void @llvm.masked.store.v8i32 30 ;AVX512: call <16 x i32> @llvm.masked.load.v16i32 32 ;AVX512: call void @llvm.masked.store.v16i32 107 ;AVX2: call <8 x float> @llvm.masked.load.v8f32 109 ;AVX2: call void @llvm.masked.store.v8f32 114 ;AVX512: call <16 x float> @llvm.masked.load.v16f32 116 ;AVX512: call void @llvm.masked.store.v16f32 192 ;AVX2: call <4 x double> @llvm.masked.load.v4f6 [all...] |
/external/llvm/lib/Target/R600/ |
CaymanInstructions.td | 110 let DST_SEL_Y = 7; // Masked 111 let DST_SEL_Z = 7; // Masked 112 let DST_SEL_W = 7; // Masked 120 let DST_SEL_Y = 7; // Masked 121 let DST_SEL_Z = 7; // Masked 122 let DST_SEL_W = 7; // Masked 132 let DST_SEL_Y = 7; // Masked 133 let DST_SEL_Z = 7; // Masked 134 let DST_SEL_W = 7; // Masked
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R600ExpandSpecialInstrs.cpp | 252 // TO_Y (write masked) = DP4 T1_Y, T2_Y 253 // TO_Z (write masked) = DP4 T1_Z, T2_Z 254 // TO_W (write masked) = DP4 T1_W, T2_W 260 // T0_Y (write masked) = MULLO_INT T1_X, T2_X 261 // T0_Z (write masked) = MULLO_INT T1_X, T2_X 262 // T0_W (write masked) = MULLO_INT T1_X, T2_X
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/external/llvm/test/CodeGen/Thumb2/ |
bfi.ll | 58 %b.masked = and i32 %b, -2 59 %and3 = or i32 %b.masked, %and
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/bionic/libm/include/amd64/machine/ |
fpu.h | 39 * with all exceptions masked.
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/development/ndk/platforms/android-21/arch-x86_64/include/machine/ |
fpu.h | 39 * with all exceptions masked.
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/external/jmdns/src/javax/jmdns/impl/constants/ |
DNSLabel.java | 76 * @return masked value
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/external/llvm/test/Transforms/InstCombine/ |
icmp-logical.ll | 131 %masked = and i32 %in, 1 132 %tst2 = icmp eq i32 %masked, 0 145 %masked = and i32 %in, 1 146 %tst1 = icmp eq i32 %masked, 0
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/prebuilts/ndk/9/platforms/android-21/arch-x86_64/usr/include/machine/ |
fpu.h | 39 * with all exceptions masked.
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/external/lzma/C/ |
Ppmd.h | 32 /* SEE-contexts for PPM-contexts with masked symbols */
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