| /external/llvm/test/CodeGen/Mips/ |
| fp64a.ll | 35 ; 32R2-NO-FP64A-LE: mthc1 $5, $f0
39 ; 32R2-NO-FP64A-BE: mthc1 $4, $f0
56 ; 32R2-NO-FP64A-LE: mthc1 $7, $f0
59 ; 32R2-NO-FP64A-BE: mthc1 $6, $f0
76 ; 32R2-NO-FP64A-LE: mthc1 $7, $f0
79 ; 32R2-NO-FP64A-BE: mthc1 $6, $f0
96 ; 32R2-NO-FP64A-LE: mthc1 $7, $f0
99 ; 32R2-NO-FP64A-BE: mthc1 $6, $f0
117 ; 32R2-NO-FP64A-LE-DAG: mthc1 $5, $[[T0:f[0-9]+]]
119 ; 32R2-NO-FP64A-LE-DAG: mthc1 $7, $[[T1:f[0-9]+]
[all...] |
| fpxx.ll | 38 ; 32R2-NOFPXX: mthc1 $5, $f0
41 ; 32R2-FPXX: mthc1 $5, $f0
63 ; 32R2-NOFPXX: mthc1 $7, $f0
66 ; 32R2-FPXX: mthc1 $7, $f0
87 ; 32R2-NOFPXX: mthc1 $7, $f0
90 ; 32R2-FPXX: mthc1 $7, $f0
111 ; 32R2-NOFPXX: mthc1 $7, $f0
114 ; 32R2-FPXX: mthc1 $7, $f0
135 ; 32R2-NOFPXX: mthc1 $zero, $f0
138 ; 32R2-FPXX: mthc1 $zero, $f
[all...] |
| 2013-11-18-fp64-const0.ll | 18 ; FIXME: A redundant mthc1 is currently emitted. Add a -NOT when it is
|
| buildpairextractelementf64.ll | 16 ; HAS-MFHC1-DAG: mthc1
|
| mno-ldc1-sdc1.ll | 63 ; 32R2-LE-PIC-DAG: mthc1 $[[R1]], $f0
68 ; 32R6-LE-PIC-DAG: mthc1 $[[R1]], $f0
82 ; 32R2-LE-STATIC-DAG: mthc1 $[[R3]], $f0
89 ; 32R6-LE-STATIC-DAG: mthc1 $[[R3]], $f0
99 ; 32R2-BE-PIC-DAG: mthc1 $[[R0]], $f0
104 ; 32R6-BE-PIC-DAG: mthc1 $[[R0]], $f0
197 ; 32R2-DAG: mthc1 $[[R1]], $f0
204 ; 32R6-DAG: mthc1 $[[R1]], $f0
|
| analyzebranch.ll | 17 ; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]]
|
| fcopysign.ll | 20 ; 32R2: mthc1 $[[INS]], $f0
|
| fmadd1.ll | 200 ; 32R2: mthc1 $zero, $[[T2]]
241 ; 32R2: mthc1 $zero, $[[T2]]
285 ; 32R2-NAN: mthc1 $zero, $[[T2]]
333 ; 32R2-NAN: mthc1 $zero, $[[T2]]
|
| select.ll | 174 ; 32R2-DAG: mthc1 $7, $[[F0]]
179 ; 32R6-DAG: mthc1 $7, $[[F0]]
471 ; 32R2-DAG: mthc1 $7, $[[F2]]
478 ; 32R6-DAG: mthc1 $7, $[[F2]]
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| ret.ll | 10 ; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
11 ; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
12 ; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
13 ; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
14 ; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
155 ; NO-MTHC1-DAG: mtc1 $zero, $f0
157 ; MTHC1-DAG: mtc1 $zero, $f0
184 ; NO-MTHC1-DAG: mtc1 $zero, $f0
185 ; NO-MTHC1-DAG: mtc1 $zero, $f1
187 ; MTHC1-DAG: mtc1 $zero, $f
[all...] |
| /art/runtime/arch/mips/ |
| asm_support_mips.S | 70 /* mips32r5 & mips32r6 have mthc1 op, and have 64-bit fp regs,
78 mthc1 \temp, \feven
93 mthc1 \rodd, \feven
97 /* mips32r1 has no mthc1 op;
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| simplestorefp1.ll | 38 ; mips32r2: mthc1 $[[REG2a]], $f[[REG3]]
|
| callabi.ll | 240 ; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
275 ; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
281 ; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f14
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 18 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/lib/Target/Mips/ |
| MicroMipsInstrFPU.td | 128 def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
|
| MipsSEFrameLowering.cpp | 263 /// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is not
270 // For fpxx and when mthc1 is not available, use:
289 // the cases where mthc1 is not available). 64-bit architectures and
|
| MipsSEInstrInfo.cpp | 560 // When mthc1 is available, use:
562 // mthc1 Hi, $fp
593 // MTHC1 is one of two instructions that are affected since they are
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 22 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 27 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 31 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| basic_operations_float.ll | 195 ; MIPS32-NOT: mthc1
216 ; MIPS32-NOT: mthc1
|
| /external/llvm/test/MC/Mips/ |
| micromips-fpu-instructions.s | 57 # CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38]
122 # CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b]
183 mthc1 $6, $f8
|
| mips-fpu-instructions.s | 173 # CHECK: mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44]
208 mthc1 $17, $f6
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 53 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | [all...] |
