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  /external/valgrind/none/tests/s390x/
spechelper-clr.stdout.exp 1 Test #1 op1 == op2
3 Test #2 op1 > op2
5 Test #3 op1 < op2
spechelper-cr.stdout.exp 1 Test #1 op1 == op2
3 Test #2 op1 > op2
5 Test #3 op1 < op2
spechelper-slgr.stdout.exp 1 Test #1 op1 == op2
3 Test #2 op1 < op2
5 Test #3 op1 > op2
spechelper-slr.stdout.exp 1 Test #1 op1 == op2
3 Test #2 op1 < op2
5 Test #3 op1 > op2
laa.stdout.exp 1 before op1 = 0
4 after op1 = 0
8 before op1 = 0xffffffff
11 after op1 = 0xffffffff
15 before op1 = 0x10000000
18 after op1 = 0x10000000
22 before op1 = 0x10000000
25 after op1 = 0x20000000
29 before op1 = 0xffffffff
32 after op1 = 0x
    [all...]
cds.stdout.exp 1 before op1 = (0x44556677, 0x111111118899aabb)
4 after op1 = (0x44556677, 0x111111118899aabb)
8 before op1 = (0x1000000000000000, 0)
11 after op1 = (0x1000000080000000, 0x1)
cs.stdout.exp 1 before op1 = 0x10000000
4 after op1 = 0x10000000
8 before op1 = 0x10000000
11 after op1 = 0x20000000
csg.stdout.exp 1 before op1 = 0x1000000000000000
4 after op1 = 0x1000000000000000
8 before op1 = 0x1000000000000000
11 after op1 = 0x2000000000000000
cds.c 15 quad_word op1 = op1_init; local
19 quad_word op1_before = op1;
23 printf("before op1 = (%#lx, %#lx)\n", op1.high, op1.low);
31 "stmg %%r0,%%r1,%1\n" // store r0,r1 to op1
35 : "=d" (cc), "+QS" (op1), "+QS" (op2), "+QS" (op3)
39 printf("after op1 = (%#lx, %#lx)\n", op1.high, op1.low)
95 quad_word op1, op3; local
    [all...]
cdsg.stdout.exp 1 before op1 = (0x11223344556677, 0x8899aabbccddeeff)
4 after op1 = (0x11223344556677, 0x8899aabbccddeeff)
8 before op1 = (0x8000000000000000, 0)
11 after op1 = (0, 0x1)
15 before op1 = (0, 0x1)
18 after op1 = (0x1, 0)
cs.c 8 register int32_t op1 asm("8") = op1_init;
14 printf("before op1 = %#x\n", op1);
22 : "=d" (cc), "+Q" (op2), "+d"(op1), "+d"(op3)
26 printf("after op1 = %#x\n", op1);
39 if (op1 != op2) {
csg.c 8 register int64_t op1 asm("8") = op1_init;
14 printf("before op1 = %#lx\n", op1);
22 : "=d" (cc), "+Q" (op2), "+d"(op1), "+d"(op3)
26 printf("after op1 = %#lx\n", op1);
39 if (op1 != op2) {
cdsg.c 28 printf("before op1 = (%#lx, %#lx)\n", _op1.high, _op1.low);
44 printf("after op1 = (%#lx, %#lx)\n", _op1.high, _op1.low);
84 quad_word op1, op2, op3; local
86 // op1 == op2
87 op1.high = 0x0011223344556677ull;
88 op1.low = 0x8899aabbccddeeffull;
89 op2 = op1;
91 test(op1, op2, op3, 0);
93 // op1 != op2 (only MSB differs)
94 op1.high = 0x8000000000000000ull
    [all...]
laa.c 8 register int32_t op1 asm("8") = op1_init;
14 printf("before op1 = %#x\n", op1);
22 : "=d" (cc), "+Q" (op2), "+d"(op1), "+d"(op3)
26 printf("after op1 = %#x\n", op1);
dfp_utils.h 22 #define DFP_BINOP_PRINT(op1, op2, result, type, op, cc) \
24 DFP_VAL_PRINT(op1, type); \
  /external/valgrind/memcheck/tests/s390x/
cdsg.c 25 "stmg %%r0,%%r1,%1\n" // store r0,r1 to op1
34 quad_word op1, op2, op3; local
36 // op1 undefined
39 test(op1, op2, op3); // complaint
44 quad_word op1, op2, op3; local
46 op1.high = op1.low = 42;
49 test(op1, op2, op3); // complaint
54 quad_word op1, op2, op3; local
56 op1.high = op1.low = 42
    [all...]
cds.c 13 quad_word op1 = op1_init; local
21 "stmg %%r0,%%r1,%1\n" // store r0,r1 to op1
23 : "=d" (cc), "+QS" (op1), "+QS" (op2), "+QS" (op3)
43 quad_word op1, op3; local
46 // op1 undefined
47 op1 = make_undefined();
50 test(op1, op2, op3); // complaint
55 quad_word op1, op3; local
58 op1.high = op1.low = 42
66 quad_word op1, op3; local
    [all...]
cs.c 8 register int32_t op1 asm("8") = op1_init;
18 : "=d" (cc), "+Q" (op2), "+d"(op1), "+d"(op3)
25 int op1, op2, op3; local
27 test(op1, 0x10000000, 0x12345678); // complaint
csg.c 8 register int64_t op1 asm("8") = op1_init;
18 : "=d" (cc), "+Q" (op2), "+d"(op1), "+d"(op3)
25 int64_t op1, op2, op3; local
27 test(op1, 0x1000000000000000ull, 0x1234567887654321ull); // complaint
  /external/llvm/test/Bitcode/
pr18704.ll 15 ; <POINTER abbrevid=4 op0=0 op1=0/>
16 ; <POINTER abbrevid=4 op0=1 op1=0/>
17 ; <ARRAY abbrevid=9 op0=6 op1=0/>
18 ; <POINTER abbrevid=4 op0=3 op1=0/>
19 ; <ARRAY abbrevid=9 op0=10 op1=0/>
20 ; <POINTER abbrevid=4 op0=5 op1=0/>
21 ; <ARRAY abbrevid=9 op0=4 op1=0/>
22 ; <POINTER abbrevid=4 op0=7 op1=0/>
23 ; <ARRAY abbrevid=9 op0=5 op1=0/>
24 ; <POINTER abbrevid=4 op0=9 op1=0/
    [all...]
function-encoding-rel-operands.ll 7 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
8 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
9 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
22 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
23 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
24 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
25 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
  /external/llvm/test/FileCheck/
simple-var-capture.txt 3 op1 r1
5 ; CHECK: op1 [[REG:r[0-9]]]
var-ref-same-line.txt 4 op1 r1, r2, r1
6 ; CHECK: op1 [[REG:r[0-9]+]], {{r[0-9]+}}, [[REG]]
  /frameworks/base/services/tests/servicestests/src/com/android/server/content/
SyncOperationTest.java 63 SyncOperation op1 = new SyncOperation(account1, 0, local
74 // Same as op1 but different time infos
86 // Same as op1 but different authority
98 // Same as op1 but different account
110 // Same as op1 but different bundle
122 assertEquals(op1.key, op2.key);
123 assertNotSame(op1.key, op3.key);
124 assertNotSame(op1.key, op4.key);
125 assertNotSame(op1.key, op5.key);
134 SyncOperation op1 = new SyncOperation(mDummy, 0, 0, SyncOperation.REASON_PERIODIC local
    [all...]
  /external/llvm/lib/Target/XCore/Disassembler/
XCoreDisassembler.cpp 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
253 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
268 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
347 unsigned Op1, Op2;
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
352 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
360 unsigned Op1, Op2;
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
365 Inst.addOperand(MCOperand::CreateImm(Op1));
    [all...]

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