| /art/disassembler/ |
| disassembler_x86.cc | 294 const char* opcode1 = ""; // Main opcode. local
316 case rm8_r8: opcode1 = #opname; store = true; has_modrm = true; byte_operand = true; break; \
317 case rm32_r32: opcode1 = #opname; store = true; has_modrm = true; break; \
318 case r8_rm8: opcode1 = #opname; load = true; has_modrm = true; byte_operand = true; break; \
319 case r32_rm32: opcode1 = #opname; load = true; has_modrm = true; break; \
320 case ax8_i8: opcode1 = #opname; ax = true; immediate_bytes = 1; byte_operand = true; break; \
321 case ax32_i32: opcode1 = #opname; ax = true; immediate_bytes = 4; break;
358 opcode1 = "push";
363 opcode1 = "pop";
369 opcode1 = "movsxd"
[all...] |
| disassembler_arm.cc | 1563 uint16_t opcode1 = instr >> 10; local
[all...] |
| /external/llvm/tools/llvm-readobj/ |
| ARMEHABIPrinter.h | 108 uint8_t Opcode1 = Opcodes[OI++ ^ 3];
110 uint16_t GPRMask = (Opcode1 << 4) | ((Opcode0 & 0x0f) << 12);
113 Opcode0, Opcode1, GPRMask ? "pop " : "refuse to unwind");
149 uint8_t Opcode1 = Opcodes[OI++ ^ 3];
152 << format("0x%02X 0x%02X ; %s", Opcode0, Opcode1,
153 ((Opcode1 & 0xf0) || Opcode1 == 0x00) ? "spare" : "pop ");
154 if (((Opcode1 & 0xf0) == 0x00) && Opcode1)
155 PrintGPR((Opcode1 & 0x0f))
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/rawdex/ |
| Opcode.java | 277 public static boolean isBetween(Opcode opcode, Opcode opcode1, Opcode opcode2) {
278 return (opcode.ordinal() >= opcode1.ordinal() && opcode.ordinal() <= opcode2.ordinal());
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrFormats.td | 68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
78 let Inst{0-5} = opcode1;
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
1068 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1072 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1095 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1100 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrFormats.td | 937 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
945 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
949 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
957 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
976 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
984 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
[all...] |
| /hardware/intel/img/psb_video/src/mrst/ |
| psb_MPEG4.c | [all...] |
| /hardware/intel/img/psb_video/src/ |
| pnw_MPEG4.c | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 247 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode1,
250 (cast<Instruction>(V)->getOpcode() == Opcode1 ||
[all...] |
