| /external/llvm/test/MC/ARM/ |
| thumb2-ldrd.s | 11 @ CHECK: error: destination operands can't be identical
12 @ CHECK: error: destination operands can't be identical
13 @ CHECK: error: destination operands can't be identical
14 @ CHECK: error: destination operands can't be identical
15 @ CHECK-NOT: error: destination operands can't be identical
|
| arm-ldrd.s | 27 // CHECK: error: destination operands must be sequential
28 // CHECK: error: destination operands must be sequential
29 // CHECK: error: destination operands must be sequential
30 // CHECK: error: destination operands must be sequential
31 // CHECK: error: destination operands must be sequential
32 // CHECK: error: destination operands must be sequential
33 // CHECK: error: destination operands must be sequential
|
| /external/clang/test/SemaOpenCL/ |
| invalid-logical-ops-1.1.cl | 10 int flaf = 0.0f && 0.0f; // expected-error {{invalid operands}}
11 int flof = 0.0f || 0.0f; // expected-error {{invalid operands}}
12 float fbaf = 0.0f & 0.0f; // expected-error {{invalid operands}}
13 float fbof = 0.0f | 0.0f; // expected-error {{invalid operands}}
14 float fbxf = 0.0f ^ 0.0f; // expected-error {{invalid operands}}
15 int flai = 0.0f && 0; // expected-error {{invalid operands}}
16 int floi = 0.0f || 0; // expected-error {{invalid operands}}
17 float ibaf = 0 & 0.0f; // expected-error {{invalid operands}}
18 float ibof = 0 | 0.0f; // expected-error {{invalid operands}}
25 int4 f4laf = f4 && 0.0f; // expected-error {{invalid operands}}
[all...] |
| invalid-logical-ops-1.2.cl | 12 float fbaf = 0.0f & 0.0f; // expected-error {{invalid operands}}
13 float fbof = 0.0f | 0.0f; // expected-error {{invalid operands}}
14 float fbxf = 0.0f ^ 0.0f; // expected-error {{invalid operands}}
17 float ibaf = 0 & 0.0f; // expected-error {{invalid operands}}
18 float ibof = 0 | 0.0f; // expected-error {{invalid operands}}
27 float4 f4baf = f4 & 0.0f; // expected-error {{invalid operands}}
28 float4 f4bof = f4 | 0.0f; // expected-error {{invalid operands}}
29 float4 f4bxf = f4 ^ 0.0f; // expected-error {{invalid operands}}
37 double fbaf = 0.0 & 0.0; // expected-error {{invalid operands}}
38 double fbof = 0.0 | 0.0; // expected-error {{invalid operands}}
[all...] |
| /external/clang/test/SemaCXX/ |
| nullptr_in_arithmetic_ops.cpp | 7 a = 0 ? nullptr + a : a + nullptr; // expected-error 2{{invalid operands to binary expression}}
8 a = 0 ? nullptr - a : a - nullptr; // expected-error 2{{invalid operands to binary expression}}
9 a = 0 ? nullptr / a : a / nullptr; // expected-error 2{{invalid operands to binary expression}}
10 a = 0 ? nullptr * a : a * nullptr; // expected-error 2{{invalid operands to binary expression}}
11 a = 0 ? nullptr >> a : a >> nullptr; // expected-error 2{{invalid operands to binary expression}}
12 a = 0 ? nullptr << a : a << nullptr; // expected-error 2{{invalid operands to binary expression}}
13 a = 0 ? nullptr % a : a % nullptr; // expected-error 2{{invalid operands to binary expression}}
14 a = 0 ? nullptr & a : a & nullptr; // expected-error 2{{invalid operands to binary expression}}
15 a = 0 ? nullptr | a : a | nullptr; // expected-error 2{{invalid operands to binary expression}}
16 a = 0 ? nullptr ^ a : a ^ nullptr; // expected-error 2{{invalid operands to binary expression}
[all...] |
| /external/valgrind/memcheck/tests/vbit-test/ |
| TODO | 1 (1) For all operators: Add a test where both operands are completely
4 (2) Add support for IROps with vector operands.
|
| /external/mesa3d/src/glsl/ |
| opt_algebraic.cpp | 96 if (ir->operands[0]->type->is_vector())
97 ir->type = ir->operands[0]->type;
99 ir->type = ir->operands[1]->type;
108 ir_rvalue *temp = ir2->operands[op2];
109 ir2->operands[op2] = ir1->operands[op1];
110 ir1->operands[op1] = temp;
113 * base types matched, and at least one of the operands of the 2
135 if (ir1->operands[0]->type->is_matrix() ||
136 ir1->operands[1]->type->is_matrix() |
[all...] |
| lower_instructions.cpp | 128 ir->operands[1] = new(ir) ir_expression(ir_unop_neg, ir->operands[1]->type,
129 ir->operands[1], NULL);
136 assert(ir->operands[1]->type->is_float());
141 ir->operands[1]->type,
142 ir->operands[1]);
146 ir->operands[1] = expr;
154 assert(ir->operands[1]->type->is_integer());
164 ir->operands[1]->type->vector_elements,
165 ir->operands[1]->type->matrix_columns)
[all...] |
| ir_validate.cpp | 231 assert(ir->operands[0]->type == ir->type);
235 assert(ir->operands[0]->type->base_type == GLSL_TYPE_BOOL);
244 assert(ir->type == ir->operands[0]->type);
251 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
252 assert(ir->type == ir->operands[0]->type);
256 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
260 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
264 assert(ir->operands[0]->type->base_type == GLSL_TYPE_INT);
268 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
272 assert(ir->operands[0]->type->base_type == GLSL_TYPE_BOOL)
[all...] |
| /external/llvm/test/Assembler/ |
| 2003-05-21-MalformedShiftCrash.ll | 3 ; RUN: grep "constexpr requires integer operands" %t
|
| generic-debug-node.ll | 10 ; CHECK-NEXT: !1 = !GenericDebugNode(tag: DW_TAG_entry_point, header: "some\00header", operands: {!0, !2, !2})
11 !1 = !GenericDebugNode(tag: 3, header: "some\00header", operands: {!0, !3, !4})
12 !2 = !GenericDebugNode(tag: 3, header: "some\00header", operands: {!{}, !3, !4})
17 !5 = !GenericDebugNode(tag: 3, operands: {})
18 !6 = !GenericDebugNode(tag: 3, header: "", operands: {})
|
| /external/clang/test/Parser/ |
| pointer-arithmetic.c | 8 int test5(int *a, int *b) { return a + b; } /* expected-error {{invalid operands}} */
9 int *test6(int *a) { return 1 - a; } /* expected-error {{invalid operands}} */
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 89 // Length is the operand length for D(L,B)-style operands, otherwise
181 // Token operands
190 // Register operands.
202 // Access register operands. Access registers aren't exposed to LLVM
208 // Immediate operands.
220 // Immediate operands with optional TLS symbol.
225 // Memory operands.
253 assert(N == 1 && "Invalid number of operands");
257 assert(N == 1 && "Invalid number of operands");
262 assert(N == 1 && "Invalid number of operands");
[all...] |
| /external/llvm/lib/Target/R600/AsmParser/ |
| AMDGPUAsmParser.cpp | 330 OperandVector &Operands, MCStreamer &Out,
334 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
336 SMLoc NameLoc, OperandVector &Operands) override;
341 OperandVector &Operands,
344 OperandMatchResultTy parseNamedBit(const char *Name, OperandVector &Operands,
349 OperandVector &Operands);
352 void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
353 void cvtDS(MCInst &Inst, const OperandVector &Operands);
354 OperandMatchResultTy parseDSOptionalOps(OperandVector &Operands);
355 OperandMatchResultTy parseDSOff01OptionalOps(OperandVector &Operands);
[all...] |
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 74 /// types. It has utility methods for emitting text based on the operands.
118 SmallVector<OpKind, 3> Operands;
121 return Operands < O.Operands;
124 return Operands == O.Operands;
127 bool empty() const { return Operands.empty(); }
130 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
131 if (Operands[i].isImm() && Operands[i].getImmCode() != 0
[all...] |
| PseudoLoweringEmitter.cpp | 89 // Normal operands should always have the same type, or we have a
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
97 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
101 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
103 OpsAdded += Insn.Operands[i].MINumOperands;
109 // Just add the operands recursively. This is almost certainly
146 if (Insn.Operands.size() != Dag->getNumArgs())
151 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
152 NumMIOperands += Insn.Operands[i].MINumOperands;
158 // If there are more operands that weren't in the DAG, they have t
[all...] |
| /external/google-breakpad/src/third_party/libdisasm/ |
| x86_insn.c | 21 if (! insn || ! insn->operands ) {
25 for (op_lst = insn->operands; op_lst; op_lst = op_lst->next ) {
42 if (! insn || ! insn->operands ) {
46 for (op_lst = insn->operands; op_lst; op_lst = op_lst->next ) {
59 if (! insn || ! insn->operands ) {
63 for (op_lst = insn->operands; op_lst; op_lst = op_lst->next ) {
73 if (! insn || ! insn->operands ) {
77 for (op_lst = insn->operands; op_lst; op_lst = op_lst->next ) {
96 if (! insn || ! insn->operands ) {
101 if ( IS_PROPER_IMM( insn->operands ) ) {
[all...] |
| ia32_implicit.h | 6 /* OK, this is a hack to deal with prefixes having implicit operands...
|
| ia32_invariant.c | 160 inv->operands[x].access = (enum x86_op_access)
162 inv->operands[x].flags = (enum x86_op_flags)
209 mode_16, &inv->operands[x]);
214 inv->operands[x].type = op_register;
222 inv->operands[x].type = op_offset;
224 inv->operands[x].flags |= op_signed |
242 inv->operands[x].type =
245 inv->operands[x].type =
248 inv->operands[x].flags |= op_signed;
250 inv->operands[x].type = op_immediate
[all...] |
| /external/llvm/test/Verifier/ |
| 2006-07-11-StoreStruct.ll | 3 ; CHECK-NOT: Instruction operands must be first-class
|
| /ndk/build/tools/toolchain-patches/gcc/ |
| 0010-Fix-PR-target-63209.patch | 28 + and target operands are the same.
38 enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[5]),
39 operands[3], operands[4]);
40 enum rtx_code rc = GET_CODE (operands[5]);
42 operands[6] = gen_rtx_REG (mode, CC_REGNUM);
45 + if (REGNO (operands[2]) != REGNO (operands[0]))
49 + rtx tmp = operands[1];
50 + operands[1] = operands[2]
[all...] |
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | [all...] |
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 31 /// MCOperand - Instances of this class represent operands of the MCInst class.
153 SmallVector<MCOperand, 8> Operands;
163 const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
164 MCOperand &getOperand(unsigned i) { return Operands[i]; }
165 unsigned getNumOperands() const { return Operands.size(); }
168 Operands.push_back(Op);
171 void clear() { Operands.clear(); }
172 size_t size() const { return Operands.size(); }
176 iterator begin() { return Operands.begin(); }
177 const_iterator begin() const { return Operands.begin();
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| 2009-07-16-InlineAsm-M-Operand.ll | 4 ; operands. We must make sure that the operand flag is found correctly.
7 ; of PowerPC "m" operands trigger this bug.
|
| /external/llvm/test/CodeGen/X86/ |
| commuted-blend-mask.ll | 3 ; When commuting the operands of a SSE blend, make sure that the resulting blend
5 ; Before, when commuting the operands to the shuffle in function @test, the backend
|
