| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| icmpa.ll | 23 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
25 ; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
44 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
46 ; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
144 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
146 ; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
163 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
165 ; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
183 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
185 ; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
[all...] |
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | [all...] |
| assembler_arm64.cc | 122 ___ Str(reg_d(source), MEM_OP(reg_x(base), offset));
256 ___ Ldr(reg_d(dest), MEM_OP(reg_x(base), offset));
278 ___ Ldr(reg_d(dest.AsDRegister()), MEM_OP(reg_x(base), offset));
350 ___ Fmov(reg_d(dst.AsDRegister()), reg_d(src.AsDRegister()));
702 fp_reg_list.Combine(reg_d(reg.AsDRegister()).code());
763 fp_reg_list.Combine(reg_d(reg.AsDRegister()).code());
|
| assembler_arm64.h | 205 static vixl::FPRegister reg_d(int code) {
|
| /external/valgrind/VEX/priv/ |
| guest_arm_toIR.c | 3396 IRTemp reg_d = newTemp(Ity_V128); local
3407 IRTemp reg_d = newTemp(Ity_I64); local
3424 IRTemp reg_d = newTemp(Ity_V128); local
3434 IRTemp reg_d = newTemp(Ity_I64); local
3451 IRTemp reg_d = newTemp(Ity_V128); local
3461 IRTemp reg_d = newTemp(Ity_I64); local
[all...] |
