| /art/compiler/dwarf/ |
| debug_frame_opcode_writer.h | 82 uint32_t reg_mask, int reg_size) {
85 for (int i = 0; reg_mask != 0u; reg_mask >>= 1, i++) {
87 int num_zeros = CTZ(reg_mask);
89 reg_mask >>= num_zeros;
97 void ALWAYS_INLINE RestoreMany(Reg reg_base, uint32_t reg_mask) {
99 for (int i = 0; reg_mask != 0u; reg_mask >>= 1, i++) {
101 int num_zeros = CTZ(reg_mask);
103 reg_mask >>= num_zeros
[all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeX86_64.c | 406 if (b & REG_MASK)
411 else if (reg_lmap[b & REG_MASK] == 4)
415 if ((b & REG_MASK) == SLJIT_UNUSED)
418 if (reg_map[b & REG_MASK] >= 8)
428 else if (reg_lmap[b & REG_MASK] == 5)
512 else if ((b & REG_MASK) != SLJIT_UNUSED) {
514 if (immb != 0 || reg_lmap[b & REG_MASK] == 5) {
522 *buf_ptr++ |= reg_lmap[b & REG_MASK];
525 *buf_ptr++ = reg_lmap[b & REG_MASK] | (reg_lmap[OFFS_REG(b)] << 3);
528 if (immb != 0 || reg_lmap[b & REG_MASK] == 5)
[all...] |
| sljitLir.c | 106 #define REG_MASK 0x3f
107 #define OFFS_REG(reg) (((reg) >> 8) & REG_MASK)
108 #define OFFS_REG_MASK (REG_MASK << 8)
111 #define FAST_IS_REG(reg) ((reg) <= REG_MASK)
113 #define SLOW_IS_REG(reg) ((reg) > 0 && (reg) <= REG_MASK)
584 (((exp) & SLJIT_MEM) && (((exp) & REG_MASK) == reg || OFFS_REG(exp) == reg))
668 SLJIT_ASSERT(FUNCTION_CHECK_IS_REG((p) & REG_MASK)); \
669 FUNCTION_ASSERT_IF_VIRTUAL((p) & REG_MASK); \
675 SLJIT_ASSERT(!((p) & ~(SLJIT_MEM | SLJIT_IMM | REG_MASK | OFFS_REG_MASK))); \
687 SLJIT_ASSERT(FUNCTION_CHECK_IS_REG((p) & REG_MASK)); \
[all...] |
| sljitNativeX86_32.c | 287 if ((b & REG_MASK) == SLJIT_UNUSED)
297 if ((b & REG_MASK) == SLJIT_SP && !(b & OFFS_REG_MASK))
368 else if ((b & REG_MASK) != SLJIT_UNUSED) {
378 *buf_ptr++ |= reg_map[b & REG_MASK];
381 *buf_ptr++ = reg_map[b & REG_MASK] | (reg_map[OFFS_REG(b)] << 3);
395 *buf_ptr++ = reg_map[b & REG_MASK] | (reg_map[OFFS_REG(b)] << 3) | (immb << 6);
|
| sljitNativeARM_32.c | [all...] |
| sljitNativeARM_64.c | 836 if ((arg & REG_MASK) && !(arg & OFFS_REG_MASK) && argw <= 255 && argw >= -256) {
840 arg &= REG_MASK;
858 | RN(arg & REG_MASK) | RM(OFFS_REG(arg)) | (argw ? (1 << 12) : 0)));
862 arg &= REG_MASK;
892 if (!(arg & REG_MASK)) {
925 if (SLJIT_UNLIKELY((flags & UPDATE) && (arg & REG_MASK))) {
929 other_r = arg & REG_MASK;
969 arg &= REG_MASK;
986 arg &= REG_MASK;
1003 FAIL_IF(push_inst(compiler, ADDI | (1 << 22) | RD(tmp_r) | RN(arg & REG_MASK) | ((argw >> 12) << 10)))
[all...] |
| sljitNativeARM_T2_32.c | 898 if ((arg & REG_MASK) && !(arg & OFFS_REG_MASK) && argw <= 0xff && argw >= -0xff) {
932 if (!(arg & REG_MASK) || argw > 0xfff || argw < -0xff)
984 if (!(arg & REG_MASK)) {
1016 if (SLJIT_UNLIKELY((flags & UPDATE) && (arg & REG_MASK))) {
[all...] |
| sljitNativePPC_common.c | 863 /* Should work when (arg & REG_MASK) == 0. */
875 FAIL_IF(push_inst(compiler, INST_CODE_AND_DST(inst, inp_flags, reg) | A(arg & REG_MASK) | B(OFFS_REG(arg))));
879 if (SLJIT_UNLIKELY(!(arg & REG_MASK)))
884 SLJIT_ASSERT((arg & REG_MASK) || !(inst & UPDATE_REQ));
902 FAIL_IF(push_inst(compiler, INST_CODE_AND_DST(inst, inp_flags, reg) | A(arg & REG_MASK) | IMM(argw)));
937 if (!(arg & REG_MASK))
971 if ((arg & REG_MASK) == tmp_r)
995 return push_inst(compiler, INST_CODE_AND_DST(inst, inp_flags, reg) | A(arg & REG_MASK) | B(tmp_r));
998 if (SLJIT_UNLIKELY(!(arg & REG_MASK)))
1002 SLJIT_ASSERT((arg & REG_MASK) || !(inst & UPDATE_REQ))
[all...] |
| sljitNativeX86_common.c | 955 if ((dst & REG_MASK) == SLJIT_R0) {
964 else if ((dst & REG_MASK) == SLJIT_R1)
1178 if ((dst & REG_MASK) != SLJIT_R0 && (dst & OFFS_REG_MASK) != TO_OFFS_REG(SLJIT_R0))
1180 else if ((dst & REG_MASK) != SLJIT_R1 && (dst & OFFS_REG_MASK) != TO_OFFS_REG(SLJIT_R1))
[all...] |
| sljitNativeSPARC_common.c | 528 if (!(flags & WRITE_BACK) || !(arg & REG_MASK)) {
536 | S1(arg & REG_MASK) | ((arg & OFFS_REG_MASK) ? S2(OFFS_REG(arg)) : IMM(argw)),
578 base = arg & REG_MASK;
[all...] |
| sljitNativeMIPS_common.c | 720 if ((!(flags & WRITE_BACK) || !(arg & REG_MASK)) && !(arg & OFFS_REG_MASK) && argw <= SIMM_MAX && argw >= SIMM_MIN) {
724 FAIL_IF(push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(arg & REG_MASK)
774 base = arg & REG_MASK;
[all...] |
| sljitNativeTILEGX_64.c | [all...] |
| /art/compiler/dex/quick/arm64/ |
| int_arm64.cc | [all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsTargetStreamer.cpp | 582 OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
|
| /external/vixl/src/vixl/a64/ |
| simulator-a64.cc | 1892 int64_t reg_mask = instr->SixtyFourBits() ? kXRegMask : kWRegMask; local
[all...] |
