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    Searched full:scavengeregister (Results 1 - 9 of 9) sorted by null

  /external/llvm/include/llvm/CodeGen/
RegisterScavenging.h 147 /// scavengeRegister - Make a register of the specific register class
151 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
153 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
154 return scavengeRegister(RegClass, MBBI, SPAdj);
  /external/llvm/lib/Target/XCore/
XCoreRegisterInfo.cpp 101 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
173 ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
178 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
  /external/llvm/lib/Target/R600/
SIPrepareScratchRegs.cpp 147 RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);
175 ScratchOffsetReg = RS.scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
SIRegisterInfo.cpp 160 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
258 SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
324 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj);
SIInstrInfo.cpp 602 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
603 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonFixupHwLoops.cpp 166 unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0);
  /external/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp 142 int scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB);
492 int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C,
541 int Reg = scavengeRegister(G, C, MBB);
  /external/llvm/lib/CodeGen/
RegisterScavenging.cpp 367 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
PrologEpilogInserter.cpp     [all...]

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