| /external/llvm/test/CodeGen/NVPTX/ |
| i1-int-to-fp.ll | 5 ; CHECK: selp
14 ; CHECK: selp
23 ; CHECK: selp
32 ; CHECK: selp
|
| inline-asm.ll | 13 ; CHECK: selp.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %p{{[0-9]+}}
14 %0 = tail call i32 asm "selp.b32 $0, $1, $2, $3;", "=r,r,r,b"(i32 %a, i32 %b, i1 %cond)
|
| compare-int.ll | 13 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
22 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
31 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
40 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
49 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
58 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
67 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
76 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
85 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
94 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]
[all...] |
| add-128bit.ll | 11 ; CHECK: selp.b64
12 ; CHECK: selp.b64
|
| shift-parts.ll | 13 ; CHECK: selp.b64
31 ; CHECK: selp.b64
|
| bug22246.ll | 9 ; CHECK: selp.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %p{{[0-9]+}}
|
| /external/clang/test/CodeGen/ |
| nvptx-inlineasm.c | 12 "selp.s32 \t%0, 1, 0, %%p2; \n\t"
|
| /external/iproute2/ip/ |
| xfrm_policy.c | 257 char *selp = NULL; local
352 if (selp)
354 selp = *argv;
570 char *selp = NULL; local
628 if (selp)
630 selp = *argv;
649 if (!selp && !indexp) {
653 if (selp && indexp)
775 char *selp = NULL; local
828 if (selp)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.td | [all...] |
| NVPTXVector.td | [all...] |
| NVPTXISelLowering.cpp | 262 // PTX does not directly support SELP of i1, so promote to i32 first
[all...] |
| NVPTXIntrinsics.td | 54 !strconcat("selp.u32 \t$dst, 1, 0, %p2; \n\t",
63 !strconcat("selp.u32 \t$dst, 1, 0, %p2; \n\t",
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target.cpp | 38 3, 3, 3, 2, 3, 3, // SET_AND,OR,XOR, SET, SELP, SLCT
78 // SET(AND,OR,XOR); SELP, SLCT
|
| nv50_ir_print.cpp | 125 "selp",
|
| /external/llvm/docs/ |
| NVPTXUsage.rst | 959 selp.f32 %f99, 0f00000000, %f98, %p15;
961 selp.f32 %f110, 0f7F800000, %f99, %p16;
|
