| /external/libhevc/common/arm64/ |
| ihevc_intra_pred_luma_vert.s | 233 sshr d24, d24,#8
236 sshr d25, d25,#8
243 sshr d24, d24,#8
246 sshr d25, d25,#8
268 sshr d24, d24,#8
271 sshr d25, d25,#8
281 sshr d24, d24,#8
284 sshr d25, d25,#8
298 sshr d24, d24,#8
301 sshr d25, d25,#
[all...] |
| ihevc_intra_pred_luma_dc.s | 138 sshr d7, d7,#32
257 sshr d3, d3,#8 //row 0 shift (prol) (first value to be ignored)
266 sshr d3, d3,#8 //row 1 shift (prol)
275 sshr d3, d3,#8 //row 2 shift (prol)
283 sshr d3, d3,#8 //row 3 shift (prol)
291 sshr d3, d3,#8 //row 4 shift (prol)
299 sshr d3, d3,#8 //row 5 shift (prol)
310 sshr d3, d3,#8 //row 6 shift (prol)
317 sshr d3, d3,#8 //row 7 shift (prol)
346 sshr d3, d3,#8 //row 9 shift (prol
[all...] |
| ihevc_intra_pred_luma_horz.s | 212 sshr v24.8h, v24.8h,#1
226 sshr v24.8h, v24.8h,#1
294 sshr v24.8h, v24.8h,#1
338 sshr v24.8h, v24.8h,#1
|
| ihevc_intra_pred_chroma_horz.s | 297 sshr v24.8h, v24.8h,#1
341 sshr v24.8h, v24.8h,#1
|
| ihevc_intra_pred_filters_luma_mode_11_to_17.s | 284 sshr v22.8h, v22.8h,#5
416 sshr v12.8h, v12.8h,#5
529 sshr v14.8h, v14.8h,#5
632 sshr v22.8h, v22.8h,#5
|
| ihevc_intra_pred_luma_mode_3_to_9.s | 164 sshr v22.8h, v22.8h,#5
296 sshr v12.8h, v12.8h,#5
408 sshr v14.8h, v14.8h,#5
503 sshr v22.8h, v22.8h,#5
|
| ihevc_intra_pred_chroma_mode_3_to_9.s | 157 sshr v22.8h, v22.8h,#5
297 sshr v25.8h, v25.8h,#5
419 sshr v14.8h, v14.8h,#5
|
| ihevc_intra_pred_filters_chroma_mode_11_to_17.s | 276 sshr v22.8h, v22.8h,#5
419 sshr v12.8h, v12.8h,#5
548 sshr v14.8h, v14.8h,#5
|
| ihevc_deblk_luma_vert.s | 531 sshr v16.8h,v16.8h,#1
589 sshr v2.8h,v2.8h,#1
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vselect.ll | 9 ; sshr.4s v0, v0, #31
|
| complex-int-to-fp.ll | 34 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
55 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
93 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
112 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
149 ; CHECK: sshr.4h [[VAL16:v[0-9]+]], [[TMP]], #8
|
| arm64-vshr.ll | 51 ; CHECK: sshr d0, d0, #63
|
| arm64-neon-simd-shift.ll | 5 ; CHECK: sshr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #3
12 ; CHECK: sshr {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #3
19 ; CHECK: sshr {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #3
26 ; CHECK: sshr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #3
33 ; CHECK: sshr {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #3
40 ; CHECK: sshr {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #3
47 ; CHECK: sshr {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #3
|
| fp16-v4-instructions.ll | 137 ; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
|
| /external/libavc/common/armv8/ |
| ih264_iquant_itrans_recon_av8.s | 169 sshr v8.4h, v1.4h, #1 // d1>>1
170 sshr v9.4h, v3.4h, #1 // d3>>1
200 sshr v18.4h, v11.4h, #1 // q0>>1
201 sshr v19.4h, v13.4h, #1 // q1>>1
357 sshr v8.4h, v1.4h, #1 // d1>>1
358 sshr v9.4h, v3.4h, #1 // d3>>1
389 sshr v18.4h, v11.4h, #1 // q0>>1
390 sshr v19.4h, v13.4h, #1 // q1>>1
641 sshr v16.8h, v9.8h, #1 //(pi2_tmp_ptr[1] >> 1)
642 sshr v17.8h, v10.8h, #1 //(pi2_tmp_ptr[2] >> 1
[all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-simd-shift.s | 8 sshr v0.8b, v1.8b, #3
9 sshr v0.4h, v1.4h, #3
10 sshr v0.2s, v1.2s, #3
11 sshr v0.16b, v1.16b, #3
12 sshr v0.8h, v1.8h, #3
13 sshr v0.4s, v1.4s, #3
14 sshr v0.2d, v1.2d, #3
15 // CHECK: sshr v0.8b, v1.8b, #3 // encoding: [0x20,0x04,0x0d,0x0f]
16 // CHECK: sshr v0.4h, v1.4h, #3 // encoding: [0x20,0x04,0x1d,0x0f]
17 // CHECK: sshr v0.2s, v1.2s, #3 // encoding: [0x20,0x04,0x3d,0x0f
[all...] |
| arm64-advsimd.s | [all...] |
| neon-scalar-shift-imm.s | 8 sshr d15, d16, #12
10 // CHECK: sshr d15, d16, #12 // encoding: [0x0f,0x06,0x74,0x5f]
|
| /external/vixl/src/vixl/a64/ |
| logic-a64.cc | 1763 LogicVRegister Simulator::sshr(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-misc.c | 382 // CHECK: sshr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #7
388 // CHECK: sshr {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #15
394 // CHECK: sshr {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #31
400 // CHECK: sshr {{d[0-9]+}}, {{d[0-9]+}}, #63
406 // CHECK: sshr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #7
412 // CHECK: sshr {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #15
418 // CHECK: sshr {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #31
424 // CHECK: sshr {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #63
[all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | [all...] |
| test-simulator-traces-a64.h | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /external/boringssl/linux-aarch64/crypto/modes/ |
| ghashv8-armx.S | 19 sshr v17.4s,v17.4s,#31 //broadcast carry bit
|
