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  /external/strace/xlat/
atomic_ops.in 9 { OR1K_ATOMIC_UMIN, "UMIN" },
atomic_ops.h 12 { OR1K_ATOMIC_UMIN, "UMIN" },
  /external/llvm/test/CodeGen/R600/
llvm.AMDGPU.umin.ll 9 %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %load)
19 %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %p1)
33 %tmp3 = tail call i32 @llvm.AMDGPU.umin(i32 %tmp2, i32 0) nounwind readnone
41 declare i32 @llvm.AMDGPU.umin(i32, i32) #1
  /external/llvm/test/CodeGen/ARM/
atomicrmw_minmax.ll 19 %old = atomicrmw umin i32* %ptr, i32 %val monotonic
atomic-op.ll 136 %11 = atomicrmw umin i32* %val2, i32 16 monotonic
146 %12 = atomicrmw umin i32* %val2, i32 %uneg monotonic
182 %0 = atomicrmw umin i16* %val, i16 16 monotonic
192 %1 = atomicrmw umin i16* %val, i16 %uneg monotonic
227 %0 = atomicrmw umin i8* %val, i8 16 monotonic
237 %1 = atomicrmw umin i8* %val, i8 %uneg monotonic
  /external/llvm/test/Transforms/IndVarSimplify/
backedge-on-min-max.ll 234 %umin.cmp = icmp ult i32 %a_len, %n
235 %umin = select i1 %umin.cmp, i32 %a_len, i32 %n
236 %entry.cond = icmp ult i32 5, %umin
252 %be.cond = icmp ult i32 %idx.inc, %umin
262 %umin.cmp = icmp ult i32 %a_len, %n
263 %umin = select i1 %umin.cmp, i32 %a_len, i32 %n
264 %entry.cond = icmp ult i32 5, %umin
280 %be.cond = icmp ult i32 %idx.inc, %umin
    [all...]
  /external/llvm/test/MC/AArch64/
neon-max-min.s 53 umin v0.8b, v1.8b, v2.8b
54 umin v0.16b, v1.16b, v2.16b
55 umin v0.4h, v1.4h, v2.4h
56 umin v0.8h, v1.8h, v2.8h
57 umin v0.2s, v1.2s, v2.2s
58 umin v0.4s, v1.4s, v2.4s
60 // CHECK: umin v0.8b, v1.8b, v2.8b // encoding: [0x20,0x6c,0x22,0x2e]
61 // CHECK: umin v0.16b, v1.16b, v2.16b // encoding: [0x20,0x6c,0x22,0x6e]
62 // CHECK: umin v0.4h, v1.4h, v2.4h // encoding: [0x20,0x6c,0x62,0x2e]
63 // CHECK: umin v0.8h, v1.8h, v2.8h // encoding: [0x20,0x6c,0x62,0x6e
    [all...]
  /external/llvm/test/CodeGen/X86/
pr5145.ll 27 %4 = atomicrmw umin i8* @sc8, i8 8 acquire
atomic-minmax-i6432.ll 35 %4 = atomicrmw umin i64* @sc64, i64 8 acquire
atomic_op.ll 91 %13 = atomicrmw umin i32* %val2, i32 1 monotonic
96 %14 = atomicrmw umin i32* %val2, i32 10 monotonic
  /external/mesa3d/src/gallium/state_trackers/d3d1x/d3d1xshader/defs/
opcodes.txt 85 umin
  /frameworks/base/rs/java/android/renderscript/
RenderScriptGL.java 88 private void validateRange(int umin, int upref, int rmin, int rmax) {
89 if (umin < rmin || umin > rmax) {
92 if (upref < umin) {
  /external/clang/test/Analysis/
additive-folding.cpp 181 unsigned uMin = INT_MIN;
183 clang_analyzer_eval(a == sMin && a != uMin); // expected-warning{{FALSE}}
184 clang_analyzer_eval(b == uMin && b != sMin); // expected-warning{{FALSE}}
  /external/llvm/test/CodeGen/AArch64/
arm64-vmax.ll 188 ;CHECK: umin.8b
191 %tmp3 = call <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
197 ;CHECK: umin.16b
200 %tmp3 = call <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
206 ;CHECK: umin.4h
209 %tmp3 = call <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
215 ;CHECK: umin.8h
218 %tmp3 = call <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
224 ;CHECK: umin.2s
227 %tmp3 = call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2
    [all...]
  /external/clang/test/CodeGen/
arm64_vMaxMin.c 25 // CHECK: call <8 x i8> @llvm.aarch64.neon.umin.v8i8(
31 // CHECK: call <16 x i8> @llvm.aarch64.neon.umin.v16i8(
74 // CHECK: call <2 x i32> @llvm.aarch64.neon.umin.v2i32(
  /external/libhevc/common/arm64/
ihevc_sao_edge_offset_class1.s 183 UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
194 UMIN v1.8h, v1.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
205 UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
208 UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
237 UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
243 UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
313 UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
319 UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
348 UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
ihevc_sao_edge_offset_class1_chroma.s 219 UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
240 UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
253 UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
256 UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
297 UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
303 UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
394 UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
406 UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
447 UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
ihevc_sao_edge_offset_class2.s 336 UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
345 UMIN v22.8h, v22.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
433 UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
438 UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
444 UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
457 UMIN v18.8h, v18.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
514 UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
520 UMIN v5.8h, v5.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
    [all...]
ihevc_sao_edge_offset_class3.s 348 UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
354 UMIN v22.8h, v22.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
452 UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
462 UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
469 UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
478 UMIN v22.8h, v22.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
544 UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
548 UMIN v22.8h, v22.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
    [all...]
ihevc_deblk_luma_horz.s 232 umin v18.8b, v20.8b , v30.8b
248 umin v18.8b, v21.8b , v16.8b
283 umin v18.8b, v19.8b , v30.8b
309 umin v18.8b, v20.8b , v30.8b
397 umin v18.8b, v21.8b , v16.8b
423 umin v18.8b, v19.8b , v30.8b
ihevc_deblk_luma_vert.s 228 umin v21.8b, v22.8b , v31.8b
259 umin v26.8b, v20.8b , v21.8b
265 umin v19.8b, v0.8b , v30.8b
295 umin v16.8b, v26.8b , v30.8b
425 umin v16.8b, v2.8b , v27.8b
436 umin v1.8b, v0.8b , v30.8b
  /external/llvm/test/CodeGen/CPP/
atomic.ll 54 %inst10 = atomicrmw umin i32* %addr, i32 %inc singlethread release
55 ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMin, {{.*}}, Release, SingleThread
  /external/llvm/lib/IR/
ConstantRange.cpp 92 APInt UMin(CR.getUnsignedMin());
93 if (UMin.isMaxValue())
95 return ConstantRange(UMin + 1, APInt::getNullValue(W));
104 APInt UMin(CR.getUnsignedMin());
105 if (UMin.isMinValue())
107 return ConstantRange(UMin, APInt::getNullValue(W));
699 APInt umin = APIntOps::umin(Other.getUnsignedMax(), getUnsignedMax());
700 if (umin.isAllOnesValue())
702 return ConstantRange(APInt::getNullValue(getBitWidth()), umin + 1)
    [all...]
  /external/mesa3d/src/gallium/auxiliary/tgsi/
tgsi_opcode_tmp.h 158 OP12(UMIN)
  /external/llvm/test/CodeGen/NVPTX/
atomics.ll 132 %ret = atomicrmw umin i32* %subr, i32 %val seq_cst
139 %ret = atomicrmw umin i64* %subr, i64 %val seq_cst

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