| /external/llvm/test/CodeGen/ARM/ |
| vldm-liveness.ll | 4 ; s1 = VLDRS [r0, 1], Q0<imp-def>
5 ; s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
6 ; s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
7 ; s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>
|
| subreg-remat.ll | 8 ; %vreg6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%vreg6
10 ; When %vreg6 spills, the VLDRS constant pool load cannot be rematerialized
34 ; %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>; mem:LD4[ConstantPool]
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| vldlane.ll | 505 ; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.)
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| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 243 case ARM::VLDRS:
614 bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||
861 case ARM::VLDRS:
[all...] |
| ARMInstrVFP.td | 94 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMBaseRegisterInfo.cpp | 506 case ARM::VLDRS: case ARM::VLDRD:
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| ARMScheduleSwift.td | [all...] |
| ARMFastISel.cpp | 501 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
[all...] |
| ARMConstantIslandPass.cpp | 773 case ARM::VLDRS:
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm32.h | 153 void vldrs(SRegister sd, const Address& ad, Condition cond = AL) OVERRIDE;
|
| assembler_arm32.cc | 987 void Arm32Assembler::vldrs(SRegister sd, const Address& ad, Condition cond) { function in class:art::arm::Arm32Assembler
[all...] |
| assembler_thumb2.h | 190 void vldrs(SRegister sd, const Address& ad, Condition cond = AL) OVERRIDE;
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| assembler_arm.h | 471 virtual void vldrs(SRegister sd, const Address& ad, Condition cond = AL) = 0;
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| assembler_thumb2.cc | 1919 void Thumb2Assembler::vldrs(SRegister sd, const Address& ad, Condition cond) { function in class:art::arm::Thumb2Assembler
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 415 * Note: The encoding map entries for vldrd and vldrs include REG_DEF_LR, even though
422 * another use of lr could be moved across a vldrd/vldrs. By setting REG_DEF_LR, we
423 * prevent that from happening. Note that we set REG_DEF_LR on all vldrd/vldrs - even those
[all...] |
