Lines Matching refs:Operand
138 // Calculate memory accessing operand for save/restore live registers.
167 __ Add(new_base, base, Operand(spill_offset + core_spill_size));
725 __ Add(index_reg, index_reg, Operand(offset_));
1421 Operand op = OperandFromMemOperand(dst);
1730 Operand rhs = InputOperandAt(instr, 1);
1802 Operand rhs = InputOperandAt(instr, 1);
1902 // shifter operand operation, the IR generating `right_reg` (input to the type
1909 Operand right_operand(0);
1913 right_operand = Operand(right_reg, helpers::ExtendFromOpKind(op_kind));
1915 right_operand = Operand(right_reg, helpers::ShiftFromOpKind(op_kind), shift_amount);
1919 // operand. Note that VIXL would still manage if it was passed by generating
1969 Operand(InputOperandAt(instruction, 1)));
2439 Operand right = InputOperandAt(compare, 1);
2493 Operand rhs = InputOperandAt(instruction, 1);
2563 __ Neg(out, Operand(out, ASR, ctz_imm));
2616 __ Sub(out, temp, Operand(temp, ASR, type == Primitive::kPrimLong ? 63 : 31));
2618 __ Sub(temp, temp, Operand(temp, ASR, type == Primitive::kPrimLong ? 63 : 31));
2867 Operand rhs = InputOperandAt(condition, 1);
4062 __ add(out.X(), out.X(), Operand(/* offset placeholder */ 0));
4318 __ Eor(OutputRegister(instruction), InputRegisterAt(instruction, 0), vixl::Operand(1));
4763 __ Subs(temp, value_reg, Operand(lower_bound));
4770 __ Subs(temp, temp, Operand(2));
4778 __ Cmp(temp, Operand(1));
4798 __ Sub(index, value_reg, Operand(lower_bound));
4804 __ Cmp(index, Operand(num_entries));
4818 __ Add(target_address, table_base, Operand(jump_offset, SXTW));
5054 __ And(temp, temp, Operand(LockWord::kReadBarrierStateMask));
5064 __ Bic(temp2, temp, Operand(LockWord::kReadBarrierStateMask));
5067 __ Add(obj, obj, Operand(temp2));
