Lines Matching defs:SP
476 __ Ld(GpuRegister(reg), SP, 0);
483 __ Sd(GpuRegister(reg), SP, 0);
493 // If V0 spills onto the stack, SP-relative offsets need to be adjusted.
497 SP,
501 SP,
505 SP,
507 __ StoreToOffset(store_type, TMP, SP, index1 + stack_offset);
526 SP,
547 // TODO: increment/decrement SP in one step instead of two or remove this comment.
556 __ Sd(reg, SP, ofs);
565 __ Sdc1(reg, SP, ofs);
577 __ Sd(kMethodRegisterArgument, SP, kCurrentMethodStackOffset);
594 // TODO: increment/decrement SP in one step instead of two or remove this comment.
601 __ Ldc1(reg, SP, ofs);
610 __ Ld(reg, SP, ofs);
669 SP,
675 SP,
751 SP,
756 SP,
778 __ StoreToOffset(store_type, gpr, SP, destination.GetStackIndex());
784 __ LoadFromOffset(kLoadWord, TMP, SP, source.GetStackIndex());
785 __ StoreToOffset(kStoreWord, TMP, SP, destination.GetStackIndex());
787 __ LoadFromOffset(kLoadDoubleword, TMP, SP, source.GetStackIndex());
788 __ StoreToOffset(kStoreDoubleword, TMP, SP, destination.GetStackIndex());
835 __ LoadFromOffset(load_type, TMP, SP, mem_loc.GetStackIndex());
839 SP,
848 __ StoreToOffset(store_type, reg_loc.AsRegister<GpuRegister>(), SP, mem_loc.GetStackIndex());
895 // ZERO, K0, K1, GP, SP, RA are always reserved and can't be allocated.
900 blocked_core_registers_[SP] = true;
930 __ StoreToOffset(kStoreDoubleword, GpuRegister(reg_id), SP, stack_index);
935 __ LoadFromOffset(kLoadDoubleword, GpuRegister(reg_id), SP, stack_index);
940 __ StoreFpuToOffset(kStoreDoubleword, FpuRegister(reg_id), SP, stack_index);
945 __ LoadFpuFromOffset(kLoadDoubleword, FpuRegister(reg_id), SP, stack_index);
2948 __ LoadFromOffset(kLoadUnsignedWord, temp, SP, receiver.GetStackIndex());
3081 __ Ld(reg, SP, kCurrentMethodStackOffset);
