Lines Matching defs:first
854 // guaranteed that the receiver is the first register of the calling convention.
2894 Location first = locations->InAt(0);
2901 if (out.AsRegister<Register>() == first.AsRegister<Register>()) {
2904 __ addl(out.AsRegister<CpuRegister>(), first.AsRegister<CpuRegister>());
2907 first.AsRegister<CpuRegister>(), second.AsRegister<CpuRegister>(), TIMES_1, 0));
2910 if (out.AsRegister<Register>() == first.AsRegister<Register>()) {
2915 first.AsRegister<CpuRegister>(), second.GetConstant()->AsIntConstant()->GetValue()));
2918 DCHECK(first.Equals(locations->Out()));
2919 __ addl(first.AsRegister<CpuRegister>(), Address(CpuRegister(RSP), second.GetStackIndex()));
2926 if (out.AsRegister<Register>() == first.AsRegister<Register>()) {
2929 __ addq(out.AsRegister<CpuRegister>(), first.AsRegister<CpuRegister>());
2932 first.AsRegister<CpuRegister>(), second.AsRegister<CpuRegister>(), TIMES_1, 0));
2939 if (out.AsRegister<Register>() == first.AsRegister<Register>()) {
2943 first.AsRegister<CpuRegister>(), int32_value));
2951 __ addss(first.AsFpuRegister<XmmRegister>(), second.AsFpuRegister<XmmRegister>());
2953 __ addss(first.AsFpuRegister<XmmRegister>(),
2958 __ addss(first.AsFpuRegister<XmmRegister>(),
2966 __ addsd(first.AsFpuRegister<XmmRegister>(), second.AsFpuRegister<XmmRegister>());
2968 __ addsd(first.AsFpuRegister<XmmRegister>(),
2973 __ addsd(first.AsFpuRegister<XmmRegister>(),
3014 Location first = locations->InAt(0);
3016 DCHECK(first.Equals(locations->Out()));
3020 __ subl(first.AsRegister<CpuRegister>(), second.AsRegister<CpuRegister>());
3023 __ subl(first.AsRegister<CpuRegister>(), imm);
3025 __ subl(first.AsRegister<CpuRegister>(), Address(CpuRegister(RSP), second.GetStackIndex()));
3033 __ subq(first.AsRegister<CpuRegister>(), Immediate(static_cast<int32_t>(value)));
3035 __ subq(first.AsRegister<CpuRegister>(), second.AsRegister<CpuRegister>());
3042 __ subss(first.AsFpuRegister<XmmRegister>(), second.AsFpuRegister<XmmRegister>());
3044 __ subss(first.AsFpuRegister<XmmRegister>(),
3049 __ subss(first.AsFpuRegister<XmmRegister>(),
3057 __ subsd(first.AsFpuRegister<XmmRegister>(), second.AsFpuRegister<XmmRegister>());
3059 __ subsd(first.AsFpuRegister<XmmRegister>(),
3064 __ subsd(first.AsFpuRegister<XmmRegister>(),
3117 Location first = locations->InAt(0);
3123 // problems where the output may not be the same as the first operand.
3126 __ imull(out.AsRegister<CpuRegister>(), first.AsRegister<CpuRegister>(), imm);
3128 DCHECK(first.Equals(out));
3129 __ imull(first.AsRegister<CpuRegister>(), second.AsRegister<CpuRegister>());
3131 DCHECK(first.Equals(out));
3133 __ imull(first.AsRegister<CpuRegister>(),
3139 // problems where the output may not be the same as the first operand.
3143 __ imulq(out.AsRegister<CpuRegister>(), first.AsRegister<CpuRegister>(),
3147 DCHECK(first.Equals(out));
3148 __ imulq(first.AsRegister<CpuRegister>(), codegen_->LiteralInt64Address(value));
3151 DCHECK(first.Equals(out));
3152 __ imulq(first.AsRegister<CpuRegister>(), second.AsRegister<CpuRegister>());
3155 DCHECK(first.Equals(out));
3156 __ imulq(first.AsRegister<CpuRegister>(),
3163 DCHECK(first.Equals(out));
3165 __ mulss(first.AsFpuRegister<XmmRegister>(), second.AsFpuRegister<XmmRegister>());
3167 __ mulss(first.AsFpuRegister<XmmRegister>(),
3172 __ mulss(first.AsFpuRegister<XmmRegister>(),
3179 DCHECK(first.Equals(out));
3181 __ mulsd(first.AsFpuRegister<XmmRegister>(), second.AsFpuRegister<XmmRegister>());
3183 __ mulsd(first.AsFpuRegister<XmmRegister>(),
3188 __ mulsd(first.AsFpuRegister<XmmRegister>(),
3226 Location first = locations->InAt(0);
3236 PushOntoFPStack(first, 0, 2 * elem_size, is_float);
3574 Location first = locations->InAt(0);
3576 DCHECK(first.Equals(locations->Out()));
3588 __ divss(first.AsFpuRegister<XmmRegister>(), second.AsFpuRegister<XmmRegister>());
3590 __ divss(first.AsFpuRegister<XmmRegister>(),
3595 __ divss(first.AsFpuRegister<XmmRegister>(),
3603 __ divsd(first.AsFpuRegister<XmmRegister>(), second.AsFpuRegister<XmmRegister>());
3605 __ divsd(first.AsFpuRegister<XmmRegister>(),
3610 __ divsd(first.AsFpuRegister<XmmRegister>(),
4712 // This first temporary register is possibly used for heap
5731 // convention), which might be cluttered by the potential first
6019 // might be cluttered by the potential first read barrier
6084 Location first = locations->InAt(0);
6086 DCHECK(first.Equals(locations->Out()));
6091 __ andl(first.AsRegister<CpuRegister>(), second.AsRegister<CpuRegister>());
6093 __ orl(first.AsRegister<CpuRegister>(), second.AsRegister<CpuRegister>());
6096 __ xorl(first.AsRegister<CpuRegister>(), second.AsRegister<CpuRegister>());
6101 __ andl(first.AsRegister<CpuRegister>(), imm);
6103 __ orl(first.AsRegister<CpuRegister>(), imm);
6106 __ xorl(first.AsRegister<CpuRegister>(), imm);
6111 __ andl(first.AsRegister<CpuRegister>(), address);
6113 __ orl(first.AsRegister<CpuRegister>(), address);
6116 __ xorl(first.AsRegister<CpuRegister>(), address);
6121 CpuRegister first_reg = first.AsRegister<CpuRegister>();
6490 // Handle the first compare/branch as a special case because it might
