Lines Matching full:scratch
59 void Arm64Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister /* scratch */) {
160 Arm64ManagedRegister scratch = m_scratch.AsArm64();
161 CHECK(scratch.IsXRegister()) << scratch;
162 LoadImmediate(scratch.AsXRegister(), imm);
163 StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(), SP,
169 Arm64ManagedRegister scratch = m_scratch.AsArm64();
170 CHECK(scratch.IsXRegister()) << scratch;
171 LoadImmediate(scratch.AsXRegister(), imm);
172 StoreToOffset(scratch.AsXRegister(), TR, offs.Int32Value());
178 Arm64ManagedRegister scratch = m_scratch.AsArm64();
179 CHECK(scratch.IsXRegister()) << scratch;
180 AddConstant(scratch.AsXRegister(), SP, fr_offs.Int32Value());
181 StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
194 Arm64ManagedRegister scratch = m_scratch.AsArm64();
196 LoadFromOffset(scratch.AsXRegister(), SP, in_off.Int32Value());
197 StoreToOffset(scratch.AsXRegister(), SP, dest_off.Int32Value() + 8);
360 Arm64ManagedRegister scratch = m_scratch.AsArm64();
361 CHECK(scratch.IsXRegister()) << scratch;
362 LoadFromOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
363 StoreToOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value());
369 Arm64ManagedRegister scratch = m_scratch.AsArm64();
370 CHECK(scratch.IsXRegister()) << scratch;
371 LoadFromOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value());
372 StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
377 Arm64ManagedRegister scratch = m_scratch.AsArm64();
378 CHECK(scratch.IsXRegister()) << scratch;
379 LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(),
381 StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(),
387 Arm64ManagedRegister scratch = m_scratch.AsArm64();
388 CHECK(scratch.IsXRegister()) << scratch;
391 LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), SP, src.Int32Value());
392 StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(), SP, dest.Int32Value());
394 LoadFromOffset(scratch.AsXRegister(), SP, src.Int32Value());
395 StoreToOffset(scratch.AsXRegister(), SP, dest.Int32Value());
403 Arm64ManagedRegister scratch = m_scratch.AsArm64();
406 CHECK(scratch.IsXRegister() || scratch.IsWRegister()) << scratch;
409 LoadWFromOffset(kLoadWord, scratch.AsWRegister(), base.AsXRegister(),
411 StoreWToOffset(kStoreWord, scratch.AsWRegister(), SP, dest.Int32Value());
413 LoadFromOffset(scratch.AsXRegister(), base.AsXRegister(), src_offset.Int32Value());
414 StoreToOffset(scratch.AsXRegister(), SP, dest.Int32Value());
422 Arm64ManagedRegister scratch = m_scratch.AsArm64();
425 CHECK(scratch.IsXRegister() || scratch.IsWRegister()) << scratch;
428 LoadWFromOffset(kLoadWord, scratch.AsWRegister(), SP, src.Int32Value());
429 StoreWToOffset(kStoreWord, scratch.AsWRegister(), base.AsXRegister(),
432 LoadFromOffset(scratch.AsXRegister(), SP, src.Int32Value());
433 StoreToOffset(scratch
447 Arm64ManagedRegister scratch = m_scratch.AsArm64();
452 CHECK(scratch.IsXRegister() || scratch.IsWRegister()) << scratch;
455 if (scratch.IsWRegister()) {
456 LoadWFromOffset(kLoadWord, scratch.AsWRegister(), src.AsXRegister(),
458 StoreWToOffset(kStoreWord, scratch.AsWRegister(), dest.AsXRegister(),
461 LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), src.AsXRegister(),
463 StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(), dest.AsXRegister(),
467 LoadFromOffset(scratch.AsXRegister(), src.AsXRegister(), src_offset.Int32Value());
468 StoreToOffset(scratch.AsXRegister(), dest.AsXRegister(), dest_offset.Int32Value());
476 ManagedRegister /*scratch*/, size_t /*size*/) {
517 Arm64ManagedRegister scratch = m_scratch.AsArm64();
519 CHECK(scratch.IsXRegister()) << scratch;
520 LoadFromOffset(scratch.AsXRegister(), base.AsXRegister(), offs.Int32Value());
521 ___ Blr(reg_x(scratch.AsXRegister()));
526 Arm64ManagedRegister scratch = m_scratch.AsArm64();
528 CHECK(scratch.IsXRegister()) << scratch;
529 // Remove base and scratch form the temp list - higher level API uses IP1, IP0.
531 temps.Exclude(reg_x(base.AsXRegister()), reg_x(scratch.AsXRegister()));
532 ___ Ldr(reg_x(scratch.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value()));
533 ___ Br(reg_x(scratch.AsXRegister()));
537 Arm64ManagedRegister scratch = m_scratch.AsArm64();
538 CHECK(scratch.IsXRegister()) << scratch;
540 LoadFromOffset(scratch.AsXRegister(), SP, base.Int32Value());
541 LoadFromOffset(scratch.AsXRegister(), scratch.AsXRegister(), offs.Int32Value());
542 ___ Blr(reg_x(scratch.AsXRegister()));
545 void Arm64Assembler::CallFromThread64(ThreadOffset<8> /*offset*/, ManagedRegister /*scratch*/) {
578 Arm64ManagedRegister scratch = m_scratch.AsArm64();
579 CHECK(scratch.IsXRegister()) << scratch;
581 LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), SP,
585 // e.g. scratch = (scratch == 0) ? 0 : (SP+handle_scope_offset)
586 ___ Cmp(reg_w(scratch.AsOverlappingWRegister()), 0);
588 AddConstant(scratch.AsXRegister(), SP, handle_scope_offset.Int32Value(), ne);
590 AddConstant(scratch.AsXRegister(), SP, handle_scope_offset.Int32Value(), al);
592 StoreToOffset(scratch.AsXRegister(), SP, out_off.Int32Value());
613 Arm64ManagedRegister scratch = m_scratch.AsArm64();
614 exception_blocks_.emplace_back(new Arm64Exception(scratch, stack_adjust));
615 LoadFromOffset(scratch.AsXRegister(), TR, Thread::ExceptionOffset<8>().Int32Value());
616 ___ Cbnz(reg_x(scratch.AsXRegister()), exception_blocks_.back()->Entry());
