Lines Matching full:vixl
594 EXPECT_TRUE(vixl::x0.Is(Arm64Assembler::reg_x(X0)));
595 EXPECT_TRUE(vixl::x1.Is(Arm64Assembler::reg_x(X1)));
596 EXPECT_TRUE(vixl::x2.Is(Arm64Assembler::reg_x(X2)));
597 EXPECT_TRUE(vixl::x3.Is(Arm64Assembler::reg_x(X3)));
598 EXPECT_TRUE(vixl::x4.Is(Arm64Assembler::reg_x(X4)));
599 EXPECT_TRUE(vixl::x5.Is(Arm64Assembler::reg_x(X5)));
600 EXPECT_TRUE(vixl::x6.Is(Arm64Assembler::reg_x(X6)));
601 EXPECT_TRUE(vixl::x7.Is(Arm64Assembler::reg_x(X7)));
602 EXPECT_TRUE(vixl::x8.Is(Arm64Assembler::reg_x(X8)));
603 EXPECT_TRUE(vixl::x9.Is(Arm64Assembler::reg_x(X9)));
604 EXPECT_TRUE(vixl::x10.Is(Arm64Assembler::reg_x(X10)));
605 EXPECT_TRUE(vixl::x11.Is(Arm64Assembler::reg_x(X11)));
606 EXPECT_TRUE(vixl::x12.Is(Arm64Assembler::reg_x(X12)));
607 EXPECT_TRUE(vixl::x13.Is(Arm64Assembler::reg_x(X13)));
608 EXPECT_TRUE(vixl::x14.Is(Arm64Assembler::reg_x(X14)));
609 EXPECT_TRUE(vixl::x15.Is(Arm64Assembler::reg_x(X15)));
610 EXPECT_TRUE(vixl::x16.Is(Arm64Assembler::reg_x(X16)));
611 EXPECT_TRUE(vixl::x17.Is(Arm64Assembler::reg_x(X17)));
612 EXPECT_TRUE(vixl::x18.Is(Arm64Assembler::reg_x(X18)));
613 EXPECT_TRUE(vixl::x19.Is(Arm64Assembler::reg_x(X19)));
614 EXPECT_TRUE(vixl::x20.Is(Arm64Assembler::reg_x(X20)));
615 EXPECT_TRUE(vixl::x21.Is(Arm64Assembler::reg_x(X21)));
616 EXPECT_TRUE(vixl::x22.Is(Arm64Assembler::reg_x(X22)));
617 EXPECT_TRUE(vixl::x23.Is(Arm64Assembler::reg_x(X23)));
618 EXPECT_TRUE(vixl::x24.Is(Arm64Assembler::reg_x(X24)));
619 EXPECT_TRUE(vixl::x25.Is(Arm64Assembler::reg_x(X25)));
620 EXPECT_TRUE(vixl::x26.Is(Arm64Assembler::reg_x(X26)));
621 EXPECT_TRUE(vixl::x27.Is(Arm64Assembler::reg_x(X27)));
622 EXPECT_TRUE(vixl::x28.Is(Arm64Assembler::reg_x(X28)));
623 EXPECT_TRUE(vixl::x29.Is(Arm64Assembler::reg_x(X29)));
624 EXPECT_TRUE(vixl::x30.Is(Arm64Assembler::reg_x(X30)));
626 EXPECT_TRUE(vixl::x19.Is(Arm64Assembler::reg_x(TR)));
627 EXPECT_TRUE(vixl::ip0.Is(Arm64Assembler::reg_x(IP0)));
628 EXPECT_TRUE(vixl::ip1.Is(Arm64Assembler::reg_x(IP1)));
629 EXPECT_TRUE(vixl::x29.Is(Arm64Assembler::reg_x(FP)));
630 EXPECT_TRUE(vixl::lr.Is(Arm64Assembler::reg_x(LR)));
631 EXPECT_TRUE(vixl::sp.Is(Arm64Assembler::reg_x(SP)));
632 EXPECT_TRUE(vixl::xzr.Is(Arm64Assembler::reg_x(XZR)));
635 EXPECT_TRUE(vixl::w0.Is(Arm64Assembler::reg_w(W0)));
636 EXPECT_TRUE(vixl::w1.Is(Arm64Assembler::reg_w(W1)));
637 EXPECT_TRUE(vixl::w2.Is(Arm64Assembler::reg_w(W2)));
638 EXPECT_TRUE(vixl::w3.Is(Arm64Assembler::reg_w(W3)));
639 EXPECT_TRUE(vixl::w4.Is(Arm64Assembler::reg_w(W4)));
640 EXPECT_TRUE(vixl::w5.Is(Arm64Assembler::reg_w(W5)));
641 EXPECT_TRUE(vixl
642 EXPECT_TRUE(vixl::w7.Is(Arm64Assembler::reg_w(W7)));
643 EXPECT_TRUE(vixl::w8.Is(Arm64Assembler::reg_w(W8)));
644 EXPECT_TRUE(vixl::w9.Is(Arm64Assembler::reg_w(W9)));
645 EXPECT_TRUE(vixl::w10.Is(Arm64Assembler::reg_w(W10)));
646 EXPECT_TRUE(vixl::w11.Is(Arm64Assembler::reg_w(W11)));
647 EXPECT_TRUE(vixl::w12.Is(Arm64Assembler::reg_w(W12)));
648 EXPECT_TRUE(vixl::w13.Is(Arm64Assembler::reg_w(W13)));
649 EXPECT_TRUE(vixl::w14.Is(Arm64Assembler::reg_w(W14)));
650 EXPECT_TRUE(vixl::w15.Is(Arm64Assembler::reg_w(W15)));
651 EXPECT_TRUE(vixl::w16.Is(Arm64Assembler::reg_w(W16)));
652 EXPECT_TRUE(vixl::w17.Is(Arm64Assembler::reg_w(W17)));
653 EXPECT_TRUE(vixl::w18.Is(Arm64Assembler::reg_w(W18)));
654 EXPECT_TRUE(vixl::w19.Is(Arm64Assembler::reg_w(W19)));
655 EXPECT_TRUE(vixl::w20.Is(Arm64Assembler::reg_w(W20)));
656 EXPECT_TRUE(vixl::w21.Is(Arm64Assembler::reg_w(W21)));
657 EXPECT_TRUE(vixl::w22.Is(Arm64Assembler::reg_w(W22)));
658 EXPECT_TRUE(vixl::w23.Is(Arm64Assembler::reg_w(W23)));
659 EXPECT_TRUE(vixl::w24.Is(Arm64Assembler::reg_w(W24)));
660 EXPECT_TRUE(vixl::w25.Is(Arm64Assembler::reg_w(W25)));
661 EXPECT_TRUE(vixl::w26.Is(Arm64Assembler::reg_w(W26)));
662 EXPECT_TRUE(vixl::w27.Is(Arm64Assembler::reg_w(W27)));
663 EXPECT_TRUE(vixl::w28.Is(Arm64Assembler::reg_w(W28)));
664 EXPECT_TRUE(vixl::w29.Is(Arm64Assembler::reg_w(W29)));
665 EXPECT_TRUE(vixl::w30.Is(Arm64Assembler::reg_w(W30)));
666 EXPECT_TRUE(vixl::w31.Is(Arm64Assembler::reg_w(WZR)));
667 EXPECT_TRUE(vixl::wzr.Is(Arm64Assembler::reg_w(WZR)));
668 EXPECT_TRUE(vixl::wsp.Is(Arm64Assembler::reg_w(WSP)));
671 EXPECT_TRUE(vixl::d0.Is(Arm64Assembler::reg_d(D0)));
672 EXPECT_TRUE(vixl::d1.Is(Arm64Assembler::reg_d(D1)));
673 EXPECT_TRUE(vixl::d2.Is(Arm64Assembler::reg_d(D2)));
674 EXPECT_TRUE(vixl::d3.Is(Arm64Assembler::reg_d(D3)));
675 EXPECT_TRUE(vixl::d4.Is(Arm64Assembler::reg_d(D4)));
676 EXPECT_TRUE(vixl::d5.Is(Arm64Assembler::reg_d(D5)));
677 EXPECT_TRUE(vixl::d6.Is(Arm64Assembler::reg_d(D6)));
678 EXPECT_TRUE(vixl::d7.Is(Arm64Assembler::reg_d(D7)));
679 EXPECT_TRUE(vixl::d8.Is(Arm64Assembler::reg_d(D8)));
680 EXPECT_TRUE(vixl::d9.Is(Arm64Assembler::reg_d(D9)));
681 EXPECT_TRUE(vixl::d10.Is(Arm64Assembler::reg_d(D10)));
682 EXPECT_TRUE(vixl::d11.Is(Arm64Assembler::reg_d(D11)));
683 EXPECT_TRUE(vixl::d12.Is(Arm64Assembler::reg_d(D12)));
684 EXPECT_TRUE(vixl::d13.Is(Arm64Assembler::reg_d(D13)));
685 EXPECT_TRUE(vixl::d14.Is(Arm64Assembler::reg_d(D14)));
686 EXPECT_TRUE(vixl::d15.Is(Arm64Assembler::reg_d(D15)));
687 EXPECT_TRUE(vixl::d16.Is(Arm64Assembler::reg_d(D16)));
688 EXPECT_TRUE(vixl::d17.Is(Arm64Assembler::reg_d(D17)));
689 EXPECT_TRUE(vixl::d18.Is(Arm64Assembler::reg_d(D18)));
690 EXPECT_TRUE(vixl::d19.Is(Arm64Assembler::reg_d(D19)));
691 EXPECT_TRUE(vixl::d20.Is(Arm64Assembler::reg_d(D20)));
692 EXPECT_TRUE(vixl::d21.Is(Arm64Assembler::reg_d(D21)));
693 EXPECT_TRUE(vixl::d22.Is(Arm64Assembler::reg_d(D22)));
694 EXPECT_TRUE(vixl::d23.Is(Arm64Assembler::reg_d(D23)));
695 EXPECT_TRUE(vixl::d24.Is(Arm64Assembler::reg_d(D24)));
696 EXPECT_TRUE(vixl::d25.Is(Arm64Assembler::reg_d(D25)));
697 EXPECT_TRUE(vixl::d26.Is(Arm64Assembler::reg_d(D26)));
698 EXPECT_TRUE(vixl::d27.Is(Arm64Assembler::reg_d(D27)));
699 EXPECT_TRUE(vixl::d28.Is(Arm64Assembler::reg_d(D28)));
700 EXPECT_TRUE(vixl::d29.Is(Arm64Assembler::reg_d(D29)));
701 EXPECT_TRUE(vixl::d30.Is(Arm64Assembler::reg_d(D30)));
702 EXPECT_TRUE(vixl::d31.Is(Arm64Assembler::reg_d(D31)));
705 EXPECT_TRUE(vixl::s0.Is(Arm64Assembler::reg_s(S0)));
706 EXPECT_TRUE(vixl::s1.Is(Arm64Assembler::reg_s(S1)));
707 EXPECT_TRUE(vixl::s2.Is(Arm64Assembler::reg_s(S2)));
708 EXPECT_TRUE(vixl::s3.Is(Arm64Assembler::reg_s(S3)));
709 EXPECT_TRUE(vixl::s4.Is(Arm64Assembler::reg_s(S4)));
710 EXPECT_TRUE(vixl::s5.Is(Arm64Assembler::reg_s(S5)));
711 EXPECT_TRUE(vixl::s6.Is(Arm64Assembler::reg_s(S6)));
712 EXPECT_TRUE(vixl::s7.Is(Arm64Assembler::reg_s(S7)));
713 EXPECT_TRUE(vixl::s8.Is(Arm64Assembler::reg_s(S8)));
714 EXPECT_TRUE(vixl::s9.Is(Arm64Assembler::reg_s(S9)));
715 EXPECT_TRUE(vixl::s10.Is(Arm64Assembler::reg_s(S10)));
716 EXPECT_TRUE(vixl::s11.Is(Arm64Assembler::reg_s(S11)));
717 EXPECT_TRUE(vixl::s12.Is(Arm64Assembler::reg_s(S12)));
718 EXPECT_TRUE(vixl::s13.Is(Arm64Assembler::reg_s(S13)));
719 EXPECT_TRUE(vixl::s14.Is(Arm64Assembler::reg_s(S14)));
720 EXPECT_TRUE(vixl::s15.Is(Arm64Assembler::reg_s(S15)));
721 EXPECT_TRUE(vixl::s16.Is(Arm64Assembler::reg_s(S16)));
722 EXPECT_TRUE(vixl::s17.Is(Arm64Assembler::reg_s(S17)));
723 EXPECT_TRUE(vixl::s18.Is(Arm64Assembler::reg_s(S18)));
724 EXPECT_TRUE(vixl::s19.Is(Arm64Assembler::reg_s(S19)));
725 EXPECT_TRUE(vixl::s20.Is(Arm64Assembler::reg_s(S20)));
726 EXPECT_TRUE(vixl::s21.Is(Arm64Assembler::reg_s(S21)));
727 EXPECT_TRUE(vixl::s22.Is(Arm64Assembler::reg_s(S22)));
728 EXPECT_TRUE(vixl::s23.Is(Arm64Assembler::reg_s(S23)));
729 EXPECT_TRUE(vixl::s24.Is(Arm64Assembler::reg_s(S24)));
730 EXPECT_TRUE(vixl::s25.Is(Arm64Assembler::reg_s(S25)));
731 EXPECT_TRUE(vixl::s26.Is(Arm64Assembler::reg_s(S26)));
732 EXPECT_TRUE(vixl::s27.Is(Arm64Assembler::reg_s(S27)));
733 EXPECT_TRUE(vixl::s28.Is(Arm64Assembler::reg_s(S28)));
734 EXPECT_TRUE(vixl::s29.Is(Arm64Assembler::reg_s(S29)));
735 EXPECT_TRUE(vixl::s30.Is(Arm64Assembler::reg_s(S30)));
736 EXPECT_TRUE(vixl::s31.Is(Arm64Assembler::reg_s(S31)));
