Lines Matching refs:Operand
341 EmitOperand(0, Operand(dst));
385 EmitOperand(dst, Operand(src));
394 EmitOperand(src, Operand(dst));
646 EmitOperand(dst, Operand(src));
655 EmitOperand(dst, Operand(src));
1042 EmitComplex(7, Operand(reg), imm);
1049 EmitOperand(reg0, Operand(reg1));
1120 EmitOperand(0, Operand(reg));
1129 EmitOperand(dst, Operand(src));
1142 EmitComplex(4, Operand(dst), imm);
1149 EmitOperand(dst, Operand(src));
1162 EmitComplex(1, Operand(dst), imm);
1169 EmitOperand(dst, Operand(src));
1182 EmitComplex(6, Operand(dst), imm);
1188 EmitComplex(0, Operand(reg), imm);
1207 EmitComplex(2, Operand(reg), imm);
1214 EmitOperand(dst, Operand(src));
1228 EmitOperand(dst, Operand(src));
1234 EmitComplex(5, Operand(reg), imm);
1269 EmitOperand(dst, Operand(src));
1280 EmitOperand(dst, Operand(src));
1285 EmitOperand(dst, Operand(src));
1307 EmitOperand(5, Operand(reg));
1321 EmitOperand(4, Operand(reg));
1335 EmitOperand(dst, Operand(src));
1341 EmitComplex(3, Operand(reg), imm);
1386 Operand(reg), imm);
1390 void X86Assembler::shll(Register operand, Register shifter) {
1391 EmitGenericShift(4, Operand(operand), shifter);
1406 EmitGenericShift(5, Operand(reg), imm);
1410 void X86Assembler::shrl(Register operand, Register shifter) {
1411 EmitGenericShift(5, Operand(operand), shifter);
1426 EmitGenericShift(7, Operand(reg), imm);
1430 void X86Assembler::sarl(Register operand, Register shifter) {
1431 EmitGenericShift(7, Operand(operand), shifter);
1482 EmitGenericShift(0, Operand(reg), imm);
1486 void X86Assembler::roll(Register operand, Register shifter) {
1487 EmitGenericShift(0, Operand(operand), shifter);
1492 EmitGenericShift(1, Operand(reg), imm);
1496 void X86Assembler::rorl(Register operand, Register shifter) {
1497 EmitGenericShift(1, Operand(operand), shifter);
1504 EmitOperand(3, Operand(reg));
1816 void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
1819 const int length = operand.length_;
1822 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
1823 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
1824 // Emit the rest of the encoded operand.
1826 EmitUint8(operand.encoding_[i]);
1828 AssemblerFixup* fixup = operand.GetFixup();
1841 const Operand& operand,
1848 EmitOperand(reg_or_opcode, operand);
1850 } else if (operand.IsRegister(EAX)) {
1856 EmitOperand(reg_or_opcode, operand);
1897 const Operand& operand,
1903 EmitOperand(reg_or_opcode, operand);
1906 EmitOperand(reg_or_opcode, operand);
1913 const Operand& operand,
1918 EmitOperand(reg_or_opcode, operand);
