Lines Matching full:address
47 void X86_64Assembler::call(const Address& address) {
49 EmitOptionalRex32(address);
51 EmitOperand(2, address);
70 void X86_64Assembler::pushq(const Address& address) {
72 EmitOptionalRex32(address);
74 EmitOperand(6, address);
98 void X86_64Assembler::popq(const Address& address) {
100 EmitOptionalRex32(address);
102 EmitOperand(0, address);
131 void X86_64Assembler::movq(const Address& dst, const Immediate& imm) {
158 void X86_64Assembler::movq(CpuRegister dst, const Address& src) {
166 void X86_64Assembler::movl(CpuRegister dst, const Address& src) {
174 void X86_64Assembler::movq(const Address& dst, CpuRegister src) {
182 void X86_64Assembler::movl(const Address& dst, CpuRegister src) {
189 void X86_64Assembler::movl(const Address& dst, const Immediate& imm) {
197 void X86_64Assembler::movntl(const Address& dst, CpuRegister src) {
205 void X86_64Assembler::movntq(const Address& dst, CpuRegister src) {
226 void X86_64Assembler::cmov(Condition c, CpuRegister dst, const Address& src, bool is64bit) {
248 void X86_64Assembler::movzxb(CpuRegister dst, const Address& src) {
268 void X86_64Assembler::movsxb(CpuRegister dst, const Address& src) {
279 void X86_64Assembler::movb(CpuRegister /*dst*/, const Address& /*src*/) {
284 void X86_64Assembler::movb(const Address& dst, CpuRegister src) {
292 void X86_64Assembler::movb(const Address& dst, const Immediate& imm) {
311 void X86_64Assembler::movzxw(CpuRegister dst, const Address& src) {
329 void X86_64Assembler::movsxw(CpuRegister dst, const Address& src) {
338 void X86_64Assembler::movw(CpuRegister /*dst*/, const Address& /*src*/) {
343 void X86_64Assembler::movw(const Address& dst, CpuRegister src) {
352 void X86_64Assembler::movw(const Address& dst, const Immediate& imm) {
364 void X86_64Assembler::leaq(CpuRegister dst, const Address& src) {
372 void X86_64Assembler::leal(CpuRegister dst, const Address& src) {
389 void X86_64Assembler::movss(XmmRegister dst, const Address& src) {
399 void X86_64Assembler::movss(const Address& dst, XmmRegister src) {
427 void X86_64Assembler::movsxd(CpuRegister dst, const Address& src) {
472 void X86_64Assembler::addss(XmmRegister dst, const Address& src) {
492 void X86_64Assembler::subss(XmmRegister dst, const Address& src) {
512 void X86_64Assembler::mulss(XmmRegister dst, const Address& src) {
532 void X86_64Assembler::divss(XmmRegister dst, const Address& src) {
542 void X86_64Assembler::flds(const Address& src) {
549 void X86_64Assembler::fsts(const Address& dst) {
556 void X86_64Assembler::fstps(const Address& dst) {
563 void X86_64Assembler::movsd(XmmRegister dst, const Address& src) {
573 void X86_64Assembler::movsd(const Address& dst, XmmRegister src) {
603 void X86_64Assembler::addsd(XmmRegister dst, const Address& src) {
623 void X86_64Assembler::subsd(XmmRegister dst, const Address& src) {
643 void X86_64Assembler::mulsd(XmmRegister dst, const Address& src) {
663 void X86_64Assembler::divsd(XmmRegister dst, const Address& src) {
693 void X86_64Assembler::cvtsi2ss(XmmRegister dst, const Address& src, bool is64bit) {
728 void X86_64Assembler::cvtsi2sd(XmmRegister dst, const Address& src, bool is64bit) {
763 void X86_64Assembler::cvtss2sd(XmmRegister dst, const Address& src) {
833 void X86_64Assembler::cvtsd2ss(XmmRegister dst, const Address& src) {
862 void X86_64Assembler::comiss(XmmRegister a, const Address& b) {
881 void X86_64Assembler::comisd(XmmRegister a, const Address& b) {
900 void X86_64Assembler::ucomiss(XmmRegister a, const Address& b) {
919 void X86_64Assembler::ucomisd(XmmRegister a, const Address& b) {
973 void X86_64Assembler::xorpd(XmmRegister dst, const Address& src) {
993 void X86_64Assembler::xorps(XmmRegister dst, const Address& src) {
1011 void X86_64Assembler::andpd(XmmRegister dst, const Address& src) {
1054 void X86_64Assembler::fldl(const Address& src) {
1061 void X86_64Assembler::fstl(const Address& dst) {
1068 void X86_64Assembler::fstpl(const Address& dst) {
1083 void X86_64Assembler::fnstcw(const Address& dst) {
1090 void X86_64Assembler::fldcw(const Address& src) {
1097 void X86_64Assembler::fistpl(const Address& dst) {
1104 void X86_64Assembler::fistps(const Address& dst) {
1111 void X86_64Assembler::fildl(const Address& src) {
1118 void X86_64Assembler::filds(const Address& src) {
1219 void X86_64Assembler::xchgl(CpuRegister reg, const Address& address) {
1221 EmitOptionalRex32(reg, address);
1223 EmitOperand(reg.LowBits(), address);
1227 void X86_64Assembler::cmpw(const Address& address, const Immediate& imm) {
1231 EmitOptionalRex32(address);
1232 EmitComplex(7, address, imm);
1252 void X86_64Assembler::cmpl(CpuRegister reg, const Address& address) {
1254 EmitOptionalRex32(reg, address);
1256 EmitOperand(reg.LowBits(), address);
1260 void X86_64Assembler::cmpl(const Address& address, CpuRegister reg) {
1262 EmitOptionalRex32(reg, address);
1264 EmitOperand(reg.LowBits(), address);
1268 void X86_64Assembler::cmpl(const Address& address
1271 EmitOptionalRex32(address);
1272 EmitComplex(7, address, imm);
1292 void X86_64Assembler::cmpq(CpuRegister reg, const Address& address) {
1294 EmitRex64(reg, address);
1296 EmitOperand(reg.LowBits(), address);
1300 void X86_64Assembler::cmpq(const Address& address, const Immediate& imm) {
1303 EmitRex64(address);
1304 EmitComplex(7, address, imm);
1316 void X86_64Assembler::addl(CpuRegister reg, const Address& address) {
1318 EmitOptionalRex32(reg, address);
1320 EmitOperand(reg.LowBits(), address);
1332 void X86_64Assembler::testl(CpuRegister reg, const Address& address) {
1334 EmitOptionalRex32(reg, address);
1336 EmitOperand(reg.LowBits(), address);
1374 void X86_64Assembler::testq(CpuRegister reg, const Address& address) {
1376 EmitRex64(reg, address);
1378 EmitOperand(reg.LowBits(), address);
1390 void X86_64Assembler::andl(CpuRegister reg, const Address& address) {
1392 EmitOptionalRex32(reg, address);
1394 EmitOperand(reg.LowBits(), address);
1421 void X86_64Assembler::andq(CpuRegister dst, const Address& src) {
1437 void X86_64Assembler::orl(CpuRegister reg, const Address& address) {
1439 EmitOptionalRex32(reg, address);
1441 EmitOperand(reg.LowBits(), address);
1468 void X86_64Assembler::orq(CpuRegister dst, const Address& src) {
1484 void X86_64Assembler::xorl(CpuRegister reg, const Address& address) {
1486 EmitOptionalRex32(reg, address);
1488 EmitOperand(reg.LowBits(), address);
1514 void X86_64Assembler::xorq(CpuRegister dst, const Address& src) {
1550 void X86_64Assembler::rex_reg_mem(bool force, bool w, Register* dst, const Address& mem) {
1572 void rex_mem_reg(bool force, bool w, Address* mem, Register* src);
1590 void X86_64Assembler::addq(CpuRegister dst, const Address& address) {
1592 EmitRex64(dst, address);
1594 EmitOperand(dst.LowBits(), address);
1607 void X86_64Assembler::addl(const Address& address, CpuRegister reg) {
1609 EmitOptionalRex32(reg, address);
1611 EmitOperand(reg.LowBits(), address);
1615 void X86_64Assembler::addl(const Address& address, const Immediate& imm) {
1617 EmitOptionalRex32(address);
1618 EmitComplex(0, address, imm);
1653 void X86_64Assembler::subq(CpuRegister reg, const Address& address) {
1655 EmitRex64(reg, address);
1657 EmitOperand(reg.LowBits() & 7, address);
1661 void X86_64Assembler::subl(CpuRegister reg, const Address& address) {
1663 EmitOptionalRex32(reg, address);
1665 EmitOperand(reg.LowBits(), address);
1733 void X86_64Assembler::imull(CpuRegister reg, const Address& address) {
1735 EmitOptionalRex32(reg, address);
1738 EmitOperand(reg.LowBits(), address);
1776 void X86_64Assembler::imulq(CpuRegister reg, const Address& address) {
1778 EmitRex64(reg, address);
1781 EmitOperand(reg.LowBits(), address);
1801 void X86_64Assembler::imull(const Address& address) {
1803 EmitOptionalRex32(address);
1805 EmitOperand(5, address);
1817 void X86_64Assembler::mull(const Address& address) {
1819 EmitOptionalRex32(address);
1821 EmitOperand(4, address);
2069 void X86_64Assembler::jmp(const Address& address) {
2071 EmitOptionalRex32(address);
2073 EmitOperand(4, address);
2128 void X86_64Assembler::cmpxchgl(const Address& address, CpuRegister reg) {
2130 EmitOptionalRex32(reg, address);
2133 EmitOperand(reg.LowBits(), address);
2137 void X86_64Assembler::cmpxchgq(const Address& address, CpuRegister reg) {
2139 EmitRex64(reg, address);
2142 EmitOperand(reg.LowBits(), address);
2207 void X86_64Assembler::bsfl(CpuRegister dst, const Address& src) {
2223 void X86_64Assembler::bsfq(CpuRegister dst, const Address& src) {
2239 void X86_64Assembler::bsrl(CpuRegister dst, const Address& src) {
2255 void X86_64Assembler::bsrq(CpuRegister dst, const Address& src) {
2272 void X86_64Assembler::popcntl(CpuRegister dst, const Address& src) {
2290 void X86_64Assembler::popcntq(CpuRegister dst, const Address& src) {
2335 movsd(dst, Address(CpuRegister(RSP), 0));
2645 cfi_.SetCurrentCFAOffset(8); // Return address on stack.
2657 // return address then method on stack.
2660 - kFramePointerSize /*return address*/;
2670 movsd(Address(CpuRegister(RSP), offset), spill.AsXmmRegister());
2677 movq(Address(CpuRegister(RSP), 0), method_reg.AsX86_64().AsCpuRegister());
2683 movq(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()),
2687 movl(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsCpuRegister());
2691 movsd(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
2694 movss(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
2711 movsd(spill.AsXmmRegister(), Address(CpuRegister(RSP), offset));
2753 movl(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
2756 movq(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
2760 movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow());
2761 movq(Address(CpuRegister(RSP), FrameOffset(offs.Int32Value()+4)),
2765 fstps(Address(CpuRegister(RSP), offs));
2767 fstpl(Address(CpuRegister(RSP), offs));
2772 movss(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
2774 movsd(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
2782 movl(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
2788 movq(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
2793 movl(Address(CpuRegister(RSP), dest), Immediate(imm)); // TODO(64) movq?
2798 gs()->movl(Address::Absolute(dest, true), Immediate(imm)); // TODO(64) movq?
2806 leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), fr_offs));
2807 gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister());
2811 gs()->movq(Address::Absolute(thr_offs, true), CpuRegister(RSP));
2826 movl(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
2829 movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
2833 movq(dest.AsRegisterPairLow(), Address(CpuRegister(RSP), src));
2834 movq(dest.AsRegisterPairHigh(), Address(CpuRegister(RSP), FrameOffset(src.Int32Value()+4)));
2837 flds(Address(CpuRegister(RSP), src));
2839 fldl(Address(CpuRegister(RSP), src));
2844 movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
2846 movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
2857 gs()->movl(dest.AsCpuRegister(), Address::Absolute(src, true));
2860 gs()->movq(dest.AsRegisterPairLow(), Address::Absolute(src, true));
2863 gs()->flds(Address::Absolute(src, true));
2865 gs()->fldl(Address::Absolute(src, true));
2870 gs()->movss(dest.AsXmmRegister(), Address::Absolute(src, true));
2872 gs()->movsd(dest.AsXmmRegister(), Address::Absolute(src, true));
2880 movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
2887 movl(dest.AsCpuRegister(), Address(base.AsX86_64().AsCpuRegister(), offs));
2897 movq(dest.AsCpuRegister(), Address(base.AsX86_64().AsCpuRegister(), offs));
2903 gs()->movq(dest.AsCpuRegister(), Address::Absolute(offs, true));
2939 fstps(Address(CpuRegister(RSP), 0));
2940 movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
2943 fstpl(Address(CpuRegister(RSP), 0));
2944 movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
2957 movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), src));
2958 movl(Address(CpuRegister(RSP), dest), scratch.AsCpuRegister());
2966 gs()->movq(scratch.AsCpuRegister(), Address::Absolute(thr_offs, true));
2976 gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister());
3002 pushq(Address(CpuRegister(RSP), src));
3003 popq(Address(dest_base.AsX86_64().AsCpuRegister(), dest_offset));
3010 movq(scratch, Address(CpuRegister(RSP), src_base));
3011 movq(scratch, Address(scratch, src_offset));
3012 movq(Address(CpuRegister(RSP), dest), scratch);
3020 pushq(Address(src.AsX86_64().AsCpuRegister(), src_offset));
3021 popq(Address(dest.AsX86_64().AsCpuRegister(), dest_offset));
3029 movq(scratch, Address(CpuRegister(RSP), src));
3030 pushq(Address(scratch, src_offset));
3031 popq(Address(scratch, dest_offset));
3047 movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3059 leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3062 leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3074 movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3077 leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3080 leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3098 movq(out_reg.AsCpuRegister(), Address(in_reg.AsCpuRegister(), 0));
3113 call(Address(base.AsCpuRegister(), offset.Int32Value()));
3119 movq(scratch, Address(CpuRegister(RSP), base));
3120 call(Address(scratch, offset));
3124 gs()->call(Address::Absolute(offset, true));
3128 gs()->movq(tr.AsX86_64().AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true));
3133 gs()->movq(scratch.AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true));
3134 movq(Address(CpuRegister(RSP), offset), scratch.AsCpuRegister());
3149 gs()->cmpl(Address::Absolute(Thread::ExceptionOffset<8>(), true), Immediate(0));
3162 __ gs()->movq(CpuRegister(RDI), Address::Absolute(Thread::ExceptionOffset<8>(), true));
3163 __ gs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), true));
