Lines Matching refs:Operand
449 EmitOperand(dst.LowBits(), Operand(src));
458 EmitOperand(src.LowBits(), Operand(dst));
682 // Emit a REX.W prefix if the operand size is 64 bits.
689 EmitOperand(dst.LowBits(), Operand(src));
697 // Emit a REX.W prefix if the operand size is 64 bits.
717 // Emit a REX.W prefix if the operand size is 64 bits.
724 EmitOperand(dst.LowBits(), Operand(src));
732 // Emit a REX.W prefix if the operand size is 64 bits.
792 // Emit a REX.W prefix if the operand size is 64 bits.
812 // Emit a REX.W prefix if the operand size is 64 bits.
1240 EmitComplex(7, Operand(reg), imm);
1248 EmitOperand(reg0.LowBits(), Operand(reg1));
1280 EmitOperand(reg0.LowBits(), Operand(reg1));
1288 EmitComplex(7, Operand(reg), imm);
1360 EmitOperand(0, Operand(reg));
1386 EmitOperand(dst.LowBits(), Operand(src));
1401 EmitComplex(4, Operand(dst), imm);
1409 EmitComplex(4, Operand(reg), imm);
1417 EmitOperand(dst.LowBits(), Operand(src));
1433 EmitOperand(dst.LowBits(), Operand(src));
1448 EmitComplex(1, Operand(dst), imm);
1456 EmitComplex(1, Operand(dst), imm);
1464 EmitOperand(dst.LowBits(), Operand(src));
1480 EmitOperand(dst.LowBits(), Operand(src));
1495 EmitComplex(6, Operand(dst), imm);
1503 EmitOperand(dst.LowBits(), Operand(src));
1511 EmitComplex(6, Operand(dst), imm);
1525 // W - 64-bit operand
1552 // W - 64-bit operand
1578 EmitComplex(0, Operand(reg), imm);
1586 EmitComplex(0, Operand(reg), imm);
1626 EmitOperand(dst.LowBits(), Operand(src));
1633 EmitComplex(5, Operand(reg), imm);
1641 EmitComplex(5, Operand(reg), imm);
1703 EmitOperand(dst.LowBits(), Operand(src));
1717 EmitOperand(dst.LowBits(), Operand(src));
1722 EmitOperand(dst.LowBits(), Operand(src));
1766 EmitOperand(dst.LowBits(), Operand(reg));
1771 EmitOperand(dst.LowBits(), Operand(reg));
1789 EmitOperand(5, Operand(reg));
1797 EmitOperand(5, Operand(reg));
1813 EmitOperand(4, Operand(reg));
1835 void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) {
1836 EmitGenericShift(false, 4, operand, shifter);
1840 void X86_64Assembler::shlq(CpuRegister operand, CpuRegister shifter) {
1841 EmitGenericShift(true, 4, operand, shifter);
1855 void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) {
1856 EmitGenericShift(false, 5, operand, shifter);
1860 void X86_64Assembler::shrq(CpuRegister operand, CpuRegister shifter) {
1861 EmitGenericShift(true, 5, operand, shifter);
1870 void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) {
1871 EmitGenericShift(false, 7, operand, shifter);
1880 void X86_64Assembler::sarq(CpuRegister operand
1881 EmitGenericShift(true, 7, operand, shifter);
1890 void X86_64Assembler::roll(CpuRegister operand, CpuRegister shifter) {
1891 EmitGenericShift(false, 0, operand, shifter);
1900 void X86_64Assembler::rorl(CpuRegister operand, CpuRegister shifter) {
1901 EmitGenericShift(false, 1, operand, shifter);
1910 void X86_64Assembler::rolq(CpuRegister operand, CpuRegister shifter) {
1911 EmitGenericShift(true, 0, operand, shifter);
1920 void X86_64Assembler::rorq(CpuRegister operand, CpuRegister shifter) {
1921 EmitGenericShift(true, 1, operand, shifter);
1929 EmitOperand(3, Operand(reg));
1937 EmitOperand(3, Operand(reg));
1953 EmitOperand(2, Operand(reg));
2377 void X86_64Assembler::EmitOperand(uint8_t reg_or_opcode, const Operand& operand) {
2380 const int length = operand.length_;
2383 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
2384 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
2385 // Emit the rest of the encoded operand.
2387 EmitUint8(operand.encoding_[i]);
2389 AssemblerFixup* fixup = operand.GetFixup();
2406 const Operand& operand,
2413 EmitOperand(reg_or_opcode, operand);
2415 } else if (operand.IsRegister(CpuRegister(RAX))) {
2421 EmitOperand(reg_or_opcode, operand);
2474 EmitOperand(reg_or_opcode, Operand(reg));
2477 EmitOperand(reg_or_opcode, Operand(reg));
2485 CpuRegister operand,
2490 EmitRex64(operand);
2492 EmitOptionalRex32(operand);
2495 EmitOperand(reg_or_opcode, Operand(operand));
2500 // W - 64-bit operand
2542 void X86_64Assembler::EmitOptionalRex32(const Operand& operand) {
2543 uint8_t rex = operand.rex();
2549 void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, const Operand& operand) {
2550 uint8_t rex = operand.rex();
2559 void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, const Operand& operand) {
2560 uint8_t rex = operand.rex();
2577 void X86_64Assembler::EmitRex64(const Operand& operand) {
2578 uint8_t rex = operand.rex();
2595 void X86_64Assembler::EmitRex64(CpuRegister dst, const Operand& operand) {
2596 uint8_t rex = 0x48 | operand.rex(); // REX.W000
2603 void X86_64Assembler::EmitRex64(XmmRegister dst, const Operand& operand) {
2604 uint8_t rex = 0x48 | operand.rex(); // REX.W000
2617 void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) {
2618 uint8_t rex = operand.rex();
