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Lines Matching refs:Operand

59 class Operand : public ValueObject {
108 // Operand can be sub classed (e.g: Address).
109 Operand() : rex_(0), length_(0), fixup_(nullptr) { }
156 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); }
158 // Get the operand encoding byte at the given index.
169 class Address : public Operand {
592 void shll(CpuRegister operand, CpuRegister shifter);
594 void shrl(CpuRegister operand, CpuRegister shifter);
596 void sarl(CpuRegister operand, CpuRegister shifter);
599 void shlq(CpuRegister operand, CpuRegister shifter);
601 void shrq(CpuRegister operand, CpuRegister shifter);
603 void sarq(CpuRegister operand, CpuRegister shifter);
659 void rorl(CpuRegister operand, CpuRegister shifter);
661 void roll(CpuRegister operand, CpuRegister shifter);
664 void rorq(CpuRegister operand, CpuRegister shifter);
666 void rolq(CpuRegister operand, CpuRegister shifter);
876 void EmitOperand(uint8_t rm, const Operand& operand);
878 void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate);
884 void EmitGenericShift(bool wide, int rm, CpuRegister operand, CpuRegister shifter);
895 void EmitOptionalRex32(const Operand& operand);
896 void EmitOptionalRex32(CpuRegister dst, const Operand& operand);
897 void EmitOptionalRex32(XmmRegister dst, const Operand& operand);
902 void EmitRex64(const Operand& operand);
904 void EmitRex64(CpuRegister dst, const Operand& operand);
905 void EmitRex64(XmmRegister dst, const Operand& operand);
911 void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand);