Lines Matching refs:vixl
42 const vixl::Instruction* instr,
43 const vixl::CPURegister& reg) {
59 void CustomDisassembler::VisitLoadLiteral(const vixl::Instruction* instr) {
76 vixl::Instr op = instr->Mask(vixl::LoadLiteralMask);
78 case vixl::LDR_w_lit:
79 case vixl::LDR_x_lit:
80 case vixl::LDRSW_x_lit: {
81 int64_t data = op == vixl::LDR_x_lit ? *reinterpret_cast<int64_t*>(data_address)
86 case vixl::LDR_s_lit:
87 case vixl::LDR_d_lit: {
88 double data = (op == vixl::LDR_s_lit) ? *reinterpret_cast<float*>(data_address)
98 void CustomDisassembler::VisitLoadStoreUnsignedOffset(const vixl::Instruction* instr) {
110 const vixl::Instruction* instr = reinterpret_cast<const vixl::Instruction*>(begin);
114 return vixl::kInstructionSize;
118 for (const uint8_t* cur = begin; cur < end; cur += vixl::kInstructionSize) {
