Lines Matching defs:a0
74 #define rARG0 a0
86 #define a0 $4 /* argument registers */
520 * a0 Thread* self
543 move rSELF, a0
544 lw a0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2)
546 EAS2(rREFS, rFP, a0
547 lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc
549 EAS1(rPC, rPC, a0) # Create direct pointer to 1st dex opcode
583 GET_OPA4(a0) # a0 <- A from 11:8
588 SET_VREG_OBJECT(a2, a0) # fp[A] <- a2
590 SET_VREG(a2, a0) # fp[A] <- a2
601 GET_OPA(a0) # a0 <- AA
606 SET_VREG_OBJECT(a2, a0) # fp[AA] <- a2
608 SET_VREG(a2, a0) # fp[AA] <- a2
619 FETCH(a0, 1) # a0 <- AAAA
624 SET_VREG_OBJECT(a2, a0) # fp[AAAA] <- a2
626 SET_VREG(a2, a0) # fp[AAAA] <- a2
639 LOAD64(a0, a1, a3) # a0/a1 <- fp[B]
641 SET_VREG64(a0, a1, a2) # fp[A] <- a0/a1
654 LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB]
656 SET_VREG64(a0, a1, a2) # fp[AA] <- a0/a1
669 LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB]
671 SET_VREG64(a0, a1, a2) # fp[AAAA] <- a0/a1
683 GET_OPA4(a0) # a0 <- A from 11:8
688 SET_VREG_OBJECT(a2, a0) # fp[A] <- a2
690 SET_VREG(a2, a0) # fp[A] <- a2
703 GET_OPA(a0) # a0 <- AA
708 SET_VREG_OBJECT(a2, a0) # fp[AA] <- a2
710 SET_VREG(a2, a0) # fp[AA] <- a2
723 FETCH(a0, 1) # a0 <- AAAA
728 SET_VREG_OBJECT(a2, a0) # fp[AAAA] <- a2
730 SET_VREG(a2, a0) # fp[AAAA] <- a2
743 lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType
744 lw a0, 0(a0) # a0 <- result.i
747 SET_VREG_OBJECT(a0, a2) # fp[AA] <- a0
749 SET_VREG(a0, a2) # fp[AA] <- a0
760 LOAD64(a0, a1, a3) # a0/a1 <- retval.j
762 SET_VREG64(a0, a1, a2) # fp[AA] <- a0/a1
775 lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType
776 lw a0, 0(a0) # a0 <- result.i
779 SET_VREG_OBJECT(a0, a2) # fp[AA] <- a0
781 SET_VREG(a0, a2) # fp[AA] <- a0
806 move a0, rSELF
828 move a0, rSELF
849 move a0, rSELF
873 move a0, rSELF
890 GET_OPA(a0) # a0 <- A+
893 and a0, a0, 15
895 SET_VREG_GOTO(a1, a0, t0) # fp[A] <- a1
902 FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended)
906 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0
914 FETCH(a0, 1) # a0 <- bbbb (low)
918 or a0, a1, a0 # a0 <- BBBBbbbb
920 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0
927 FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended)
929 sll a0, a0, 16 # a0 <- BBBB0000
932 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0
939 FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended)
941 sra a1, a0, 31 # a1 <- ssssssss
944 SET_VREG64(a0, a1, a3) # vAA <- a0/a1
952 FETCH(a0, 1) # a0 <- 0000bbbb (low)
957 or a0, a0, a2 # a0 <- BBBBbbbb
958 sra a1, a0, 31 # a1 <- ssssssss
960 SET_VREG64(a0, a1, a3) # vAA <- a0/a1
968 FETCH(a0, 1) # a0 <- bbbb (low)
972 or a0, a1 # a0 <- BBBBbbbb (low word)
979 SET_VREG64(a0, a1, t1) # vAA <- a0/a1
989 li a0, 0 # a0 <- 00000000
993 SET_VREG64(a0, a1, a3) # vAA <- a0/a1
1002 FETCH(a0, 1) # a0 <- BBBB
1019 FETCH(a0, 1) # a0 <- bbbb (low)
1023 or a0, a0, a2 # a0 <- BBBBbbbb
1039 FETCH(a0, 1) # a0 <- BBBB
1060 GET_VREG(a0, a2) # a0 <- vAA (object)
1082 GET_VREG(a0, a2) # a0 <- vAA (object)
1099 FETCH(a0, 1) # a0 <- BBBB
1123 FETCH(a0, 1) # a0 <- CCCC
1146 GET_VREG(a0, a1) # a0 <- vB (object ref)
1148 beqz a0, common_errNullObject # yup, fail
1150 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- array length
1163 addu a0, rFP, OFF_FP_SHADOWFRAME
1185 addu a0, rFP, OFF_FP_SHADOWFRAME
1208 addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame
1231 addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame
1247 FETCH(a0, 1) # a0 <- bbbb (lo)
1251 or a1, a0, a1 # a1 <- BBBBbbbb
1252 GET_VREG(a0, a3) # a0 <- vAA (array object)
1288 sll a0, rINST, 16 # a0 <- AAxx0000
1289 sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended)
1291 move a0, rSELF
1306 sll a0, rINST, 16 # a0 <- AAxx0000
1307 sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended)
1333 move a0, rSELF
1373 FETCH(a0, 1) # a0 <- aaaa (lo)
1376 or rINST, a0, a1 # rINST <- AAAAaaaa
1378 move a0, rSELF
1392 FETCH(a0, 1) # a0 <- aaaa (lo)
1395 or rINST, a0, a1 # rINST <- AAAAaaaa
1421 FETCH(a0, 1) # a0 <- bbbb (lo)
1425 or a0, a0, t0 # a0 <- BBBBbbbb
1427 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2
1428 JAL(MterpDoPackedSwitch) # a0 <- code-unit branch offset
1431 move a0, rSELF
1442 FETCH(a0, 1) # a0 <- bbbb (lo)
1446 or a0, a0, t0 # a0 <- BBBBbbbb
1448 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2
1449 JAL(MterpDoPackedSwitch) # a0 <- code-unit branch offset
1478 FETCH(a0, 1) # a0 <- bbbb (lo)
1482 or a0, a0, t0 # a0 <- BBBBbbbb
1484 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2
1485 JAL(MterpDoSparseSwitch) # a0 <- code-unit branch offset
1488 move a0, rSELF
1499 FETCH(a0, 1) # a0 <- bbbb (lo)
1503 or a0, a0, t0 # a0 <- BBBBbbbb
1505 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2
1506 JAL(MterpDoSparseSwitch) # a0 <- code-unit branch offset
1546 FETCH(a0, 1) # a0 <- CCBB
1547 and a2, a0, 255 # a2 <- BB
1548 srl a3, a0, 8
1602 FETCH(a0, 1) # a0 <- CCBB
1603 and a2, a0, 255 # a2 <- BB
1604 srl a3, a0, 8
1649 FETCH(a0, 1) # a0 <- CCBB
1650 and rOBJ, a0, 255 # s5 <- BB
1651 srl t0, a0, 8 # t0 <- CC
1698 FETCH(a0, 1) # a0 <- CCBB
1699 and rOBJ, a0, 255 # s5 <- BB
1700 srl t0, a0, 8 # t0 <- CC
1746 FETCH(a0, 1) # a0 <- CCBB
1748 and a2, a0, 255 # a2 <- BB
1749 srl a3, a0, 8 # a3 <- CC
1752 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
1761 sltu t0, a0, a2 # compare lo
1762 sgtu t1, a0, a2
1782 GET_OPA4(a0) # a0 <- A+
1785 GET_VREG(a2, a0) # a2 <- vA
1794 move a0, rSELF
1821 GET_OPA4(a0) # a0 <- A+
1824 GET_VREG(a2, a0) # a2 <- vA
1833 move a0, rSELF
1860 GET_OPA4(a0) # a0 <- A+
1863 GET_VREG(a2, a0) # a2 <- vA
1872 move a0, rSELF
1899 GET_OPA4(a0) # a0 <- A+
1902 GET_VREG(a2, a0) # a2 <- vA
1911 move a0, rSELF
1938 GET_OPA4(a0) # a0 <- A+
1941 GET_VREG(a2, a0) # a2 <- vA
1950 move a0, rSELF
1977 GET_OPA4(a0) # a0 <- A+
1980 GET_VREG(a2, a0) # a2 <- vA
1989 move a0, rSELF
2016 GET_OPA(a0) # a0 <- AA
2017 GET_VREG(a2, a0) # a2 <- vAA
2026 move a0, rSELF
2055 GET_OPA(a0) # a0 <- AA
2056 GET_VREG(a2, a0) # a2 <- vAA
2065 move a0, rSELF
2094 GET_OPA(a0) # a0 <- AA
2095 GET_VREG(a2, a0) # a2 <- vAA
2104 move a0, rSELF
2133 GET_OPA(a0) # a0 <- AA
2134 GET_VREG(a2, a0) # a2 <- vAA
2143 move a0, rSELF
2172 GET_OPA(a0) # a0 <- AA
2173 GET_VREG(a2, a0) # a2 <- vAA
2182 move a0, rSELF
2211 GET_OPA(a0) # a0 <- AA
2212 GET_VREG(a2, a0) # a2 <- vAA
2221 move a0, rSELF
2322 GET_VREG(a0, a2) # a0 <- vBB (array object)
2325 beqz a0, common_errNullObject # yes, bail
2326 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2328 EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width
2330 addu a0, a0, a1
2335 lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2349 FETCH(a0, 1) # a0 <- CCBB
2351 and a2, a0, 255 # a2 <- BB
2352 srl a3, a0, 8 # a3 <- CC
2353 GET_VREG(a0, a2) # a0 <- vBB (array object)
2356 beqz a0, common_errNullObject # yes, bail
2357 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2358 EAS3(a0, a0, a1) # a0 <- arrayObj + index*width
2362 LOAD64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET)
2380 GET_VREG(a0, a2) # a0 <- vBB (array object)
2411 GET_VREG(a0, a2) # a0 <- vBB (array object)
2414 beqz a0, common_errNullObject # yes, bail
2415 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2417 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width
2419 addu a0, a0, a1
2424 lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2449 GET_VREG(a0, a2) # a0 <- vBB (array object)
2452 beqz a0, common_errNullObject # yes, bail
2453 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2455 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width
2457 addu a0, a0, a1
2462 lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2487 GET_VREG(a0, a2) # a0 <- vBB (array object)
2490 beqz a0, common_errNullObject # yes, bail
2491 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2493 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width
2495 addu a0, a0, a1
2500 lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2525 GET_VREG(a0, a2) # a0 <- vBB (array object)
2528 beqz a0, common_errNullObject # yes, bail
2529 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2531 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width
2533 addu a0, a0, a1
2538 lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2560 GET_VREG(a0, a2) # a0 <- vBB (array object)
2563 beqz a0, common_errNullObject # yes, bail
2564 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2566 EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width
2568 addu a0, a0, a1
2574 sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2587 FETCH(a0, 1) # a0 <- CCBB
2589 and a2, a0, 255 # a2 <- BB
2590 srl a3, a0, 8 # a3 <- CC
2591 GET_VREG(a0, a2) # a0 <- vBB (array object)
2594 beqz a0, common_errNullObject # yes, bail
2595 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2596 EAS3(a0, a0, a1) # a0 <- arrayObj + index*width
2604 STORE64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) # a2/a3 <- vBB[vCC]
2617 addu a0, rFP, OFF_FP_SHADOWFRAME
2644 GET_VREG(a0, a2) # a0 <- vBB (array object)
2647 beqz a0, common_errNullObject # yes, bail
2648 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2650 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width
2652 addu a0, a0, a1
2658 sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2680 GET_VREG(a0, a2) # a0 <- vBB (array object)
2683 beqz a0, common_errNullObject # yes, bail
2684 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2686 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width
2688 addu a0, a0, a1
2694 sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2716 GET_VREG(a0, a2) # a0 <- vBB (array object)
2719 beqz a0, common_errNullObject # yes, bail
2720 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2722 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width
2724 addu a0, a0, a1
2730 sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2752 GET_VREG(a0, a2) # a0 <- vBB (array object)
2755 beqz a0, common_errNullObject # yes, bail
2756 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2758 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width
2760 addu a0, a0, a1
2766 sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2780 FETCH(a0, 1) # a0 <- field ref CCCC
2809 FETCH(a0, 1) # a0 <- field byte offset
2835 FETCH(a0, 1) # a0 <- field ref CCCC
2866 FETCH(a0, 1) # a0 <- field ref CCCC
2897 FETCH(a0, 1) # a0 <- field ref CCCC
2928 FETCH(a0, 1) # a0 <- field ref CCCC
2959 FETCH(a0, 1) # a0 <- field ref CCCC
2991 FETCH(a0, 1) # a0 <- field ref CCCC
3011 FETCH(a0, 1) # a0 <- field ref CCCC
3035 addu a0, rFP, OFF_FP_SHADOWFRAME
3058 FETCH(a0, 1) # a0 <- field ref CCCC
3085 FETCH(a0, 1) # a0 <- field ref CCCC
3112 FETCH(a0, 1) # a0 <- field ref CCCC
3139 FETCH(a0, 1) # a0 <- field ref CCCC
3165 FETCH(a0, 1) # a0 <- field ref BBBB
3192 FETCH(a0, 1) # a0 <- field ref BBBB
3217 FETCH(a0, 1) # a0 <- field ref BBBB
3248 FETCH(a0, 1) # a0 <- field ref BBBB
3279 FETCH(a0, 1) # a0 <- field ref BBBB
3310 FETCH(a0, 1) # a0 <- field ref BBBB
3341 FETCH(a0, 1) # a0 <- field ref BBBB
3370 FETCH(a0, 1) # a0 <- field ref BBBB
3392 FETCH(a0, 1) # a0 <- field ref CCCC
3415 addu a0, rFP, OFF_FP_SHADOWFRAME
3437 FETCH(a0, 1) # a0 <- field ref BBBB
3462 FETCH(a0, 1) # a0 <- field ref BBBB
3487 FETCH(a0, 1) # a0 <- field ref BBBB
3512 FETCH(a0, 1) # a0 <- field ref BBBB
3537 move a0, rSELF
3562 move a0, rSELF
3587 move a0, rSELF
3612 move a0, rSELF
3637 move a0, rSELF
3655 move a0, rSELF
3676 move a0, rSELF
3701 move a0, rSELF
3726 move a0, rSELF
3751 move a0, rSELF
3776 move a0, rSELF
3818 * specifies an instruction that performs "result = op a0".
3827 GET_VREG(a0, a3) # a0 <- vB
3830 negu a0, a0 # a0 <- op, a0-a3 changed
3832 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
3843 * specifies an instruction that performs "result = op a0".
3852 GET_VREG(a0, a3) # a0 <- vB
3855 not a0, a0 # a0 <- op, a0-a3 changed
3857 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
3868 * specifies an instruction that performs "result = op a0/a1".
3877 LOAD64(a0, a1, a3) # a0/a1 <- vAA
3879 negu v0, a0 # optional op
3880 negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0 # a0/a1 <- op, a2-a3 changed
3882 SET_VREG64(v0, v1, rOBJ) # vAA <- a0/a1
3894 * specifies an instruction that performs "result = op a0/a1".
3903 LOAD64(a0, a1, a3) # a0/a1 <- vAA
3905 not a0, a0 # optional op
3906 not a1, a1 # a0/a1 <- op, a2-a3 changed
3908 SET_VREG64(a0, a1, rOBJ) # vAA <- a0/a1
3920 * specifies an instruction that performs "result = op a0".
3929 GET_VREG(a0, a3) # a0 <- vB
3932 addu a0, a0, 0x80000000 # a0 <- op, a0-a3 changed
3934 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
3945 * specifies an instruction that performs "result = op a0/a1".
3954 LOAD64(a0, a1, a3) # a0/a1 <- vAA
3957 addu a1, a1, 0x80000000 # a0/a1 <- op, a2-a3 changed
3959 SET_VREG64(a0, a1, rOBJ) # vAA <- a0/a1
3971 * that specifies an instruction that performs "result = op a0", where
3972 * "result" is a 64-bit quantity in a0/a1.
3979 GET_VREG(a0, a3) # a0 <- vB
3982 sra a1, a0, 31 # result <- op, a0-a3 changed
3984 SET_VREG64(a0, a1, rOBJ) # vA/vA+1 <- a0/a1
3996 * specifies an instruction that performs "result = op a0".
4021 * that specifies an instruction that performs "result = op a0", where
4022 * "result" is a 64-bit quantity in a0/a1.
4034 SET_VREG64_F(fv0, fv0f, rOBJ) # vA/vA+1 <- a0/a1
4048 GET_OPA4(a0) # a0 <- A from 11:8
4053 SET_VREG_OBJECT(a2, a0) # fp[A] <- a2
4055 SET_VREG(a2, a0) # fp[A] <- a2
4067 * that specifies an instruction that performs "result = op a0/a1", where
4068 * "result" is a 32-bit quantity in a0.
4097 * specifies an instruction that performs "result = op a0/a1".
4109 JAL(__floatdidf) # a0/a1 <- op, a2-a3 changed
4112 SET_VREG64_F(fv0, fv0f, rOBJ) # vAA <- a0/a1
4125 * specifies an instruction that performs "result = op a0".
4150 * that specifies an instruction that performs "result = op a0", where
4151 * "result" is a 64-bit quantity in a0/a1.
4163 SET_VREG64(rRESULT0, rRESULT1, rOBJ) # vA/vA+1 <- a0/a1
4175 * that specifies an instruction that performs "result = op a0", where
4176 * "result" is a 64-bit quantity in a0/a1.
4188 SET_VREG64_F(fv0, fv0f, rOBJ) # vA/vA+1 <- a0/a1
4200 * that specifies an instruction that performs "result = op a0/a1", where
4201 * "result" is a 32-bit quantity in a0.
4223 * Convert the double in a0/a1 to an int in a0.
4237 * specifies an instruction that performs "result = op a0/a1".
4249 b d2l_doconv # a0/a1 <- op, a2-a3 changed
4252 SET_VREG64(rRESULT0, rRESULT1, rOBJ) # vAA <- a0/a1
4265 * that specifies an instruction that performs "result = op a0/a1", where
4266 * "result" is a 32-bit quantity in a0.
4295 * specifies an instruction that performs "result = op a0".
4304 GET_VREG(a0, a3) # a0 <- vB
4306 sll a0, a0, 24 # optional op
4307 sra a0, a0, 24 # a0 <- op, a0-a3 changed
4309 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
4320 * specifies an instruction that performs "result = op a0".
4329 GET_VREG(a0, a3) # a0 <- vB
4332 and a0, 0xffff # a0 <- op, a0-a3 changed
4334 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
4345 * specifies an instruction that performs "result = op a0".
4354 GET_VREG(a0, a3) # a0 <- vB
4356 sll a0, 16 # optional op
4357 sra a0, 16 # a0 <- op, a0-a3 changed
4359 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
4370 * specifies an instruction that performs "result = a0 op a1".
4372 * comes back in a register other than a0, you can override "result".)
4383 FETCH(a0, 1) # a0 <- CCBB
4385 srl a3, a0, 8 # a3 <- CC
4386 and a2, a0, 255 # a2 <- BB
4388 GET_VREG(a0, a2) # a0 <- vBB
4396 addu a0, a0, a1 # a0 <- op, a0-a3 changed
4398 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4409 * specifies an instruction that performs "result = a0 op a1".
4411 * comes back in a register other than a0, you can override "result".)
4422 FETCH(a0, 1) # a0 <- CCBB
4424 srl a3, a0, 8 # a3 <- CC
4425 and a2, a0, 255 # a2 <- BB
4427 GET_VREG(a0, a2) # a0 <- vBB
4435 subu a0, a0, a1 # a0 <- op, a0-a3 changed
4437 SET_VREG_GOTO(a0a0
4448 * specifies an instruction that performs "result = a0 op a1".
4450 * comes back in a register other than a0, you can override "result".)
4461 FETCH(a0, 1) # a0 <- CCBB
4463 srl a3, a0, 8 # a3 <- CC
4464 and a2, a0, 255 # a2 <- BB
4466 GET_VREG(a0, a2) # a0 <- vBB
4474 mul a0, a0, a1 # a0 <- op, a0-a3 changed
4476 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4488 * specifies an instruction that performs "result = a0 op a1".
4490 * comes back in a register other than a0, you can override "result".)
4501 FETCH(a0, 1) # a0 <- CCBB
4503 srl a3, a0, 8 # a3 <- CC
4504 and a2, a0, 255 # a2 <- BB
4506 GET_VREG(a0, a2) # a0 <- vBB
4514 div a0, a0, a1 # a0 <- op, a0-a3 changed
4516 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4523 * specifies an instruction that performs "result = a0 op a1".
4525 * comes back in a register other than a0, you can override "result".)
4536 FETCH(a0, 1) # a0 <- CCBB
4538 srl a3, a0, 8 # a3 <- CC
4539 and a2, a0, 255 # a2 <- BB
4541 GET_VREG(a0, a2) # a0 <- vBB
4548 div zero, a0, a1 # optional op
4549 mflo a0 # a0 <- op, a0-a3 changed
4551 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4564 * specifies an instruction that performs "result = a0 op a1".
4566 * comes back in a register other than a0, you can override "result".)
4577 FETCH(a0, 1) # a0 <- CCBB
4579 srl a3, a0, 8 # a3 <- CC
4580 and a2, a0, 255 # a2 <- BB
4582 GET_VREG(a0, a2) # a0 <- vBB
4590 mod a0, a0, a1 # a0 <- op, a0-a3 changed
4592 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4599 * specifies an instruction that performs "result = a0 op a1".
4601 * comes back in a register other than a0, you can override "result".)
4612 FETCH(a0, 1) # a0 <- CCBB
4614 srl a3, a0, 8 # a3 <- CC
4615 and a2, a0, 255 # a2 <- BB
4617 GET_VREG(a0, a2) # a0 <- vBB
4624 div zero, a0, a1 # optional op
4625 mfhi a0 # a0 <- op, a0-a3 changed
4627 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4639 * specifies an instruction that performs "result = a0 op a1".
4641 * comes back in a register other than a0, you can override "result".)
4652 FETCH(a0, 1) # a0 <- CCBB
4654 srl a3, a0, 8 # a3 <- CC
4655 and a2, a0, 255 # a2 <- BB
4657 GET_VREG(a0, a2) # a0 <- vBB
4665 and a0, a0, a1 # a0 <- op, a0-a3 changed
4667 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4678 * specifies an instruction that performs "result = a0 op a1".
4680 * comes back in a register other than a0, you can override "result".)
4691 FETCH(a0, 1) # a0 <- CCBB
4693 srl a3, a0, 8 # a3 <- CC
4694 and a2, a0, 255 # a2 <- BB
4696 GET_VREG(a0, a2) # a0 <- vBB
4704 or a0, a0, a1 # a0 <- op, a0-a3 changed
4706 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4717 * specifies an instruction that performs "result = a0 op a1".
4719 * comes back in a register other than a0, you can override "result".)
4730 FETCH(a0, 1) # a0 <- CCBB
4732 srl a3, a0, 8 # a3 <- CC
4733 and a2, a0, 255 # a2 <- BB
4735 GET_VREG(a0, a2) # a0 <- vBB
4743 xor a0, a0, a1 # a0 <- op, a0-a3 changed
4745 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4756 * specifies an instruction that performs "result = a0 op a1".
4758 * comes back in a register other than a0, you can override "result".)
4769 FETCH(a0, 1) # a0 <- CCBB
4771 srl a3, a0, 8 # a3 <- CC
4772 and a2, a0, 255 # a2 <- BB
4774 GET_VREG(a0, a2) # a0 <- vBB
4782 sll a0, a0, a1 # a0 <- op, a0-a3 changed
4784 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4795 * specifies an instruction that performs "result = a0 op a1".
4797 * comes back in a register other than a0, you can override "result".)
4808 FETCH(a0, 1) # a0 <- CCBB
4810 srl a3, a0, 8 # a3 <- CC
4811 and a2, a0, 255 # a2 <- BB
4813 GET_VREG(a0, a2) # a0 <- vBB
4821 sra a0, a0, a1 # a0 <- op, a0-a3 changed
4823 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4834 * specifies an instruction that performs "result = a0 op a1".
4836 * comes back in a register other than a0, you can override "result".)
4847 FETCH(a0, 1) # a0 <- CCBB
4849 srl a3, a0, 8 # a3 <- CC
4850 and a2, a0, 255 # a2 <- BB
4852 GET_VREG(a0, a2) # a0 <- vBB
4860 srl a0, a0, a1 # a0 <- op, a0-a3 changed
4862 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4872 * [v1 v0] = [a1 a0] + [a3 a2];
4873 * addu v0,a2,a0
4881 * specifies an instruction that performs "result = a0-a1 op a2-a3".
4883 * comes back in a register other than a0, you can override "result".)
4894 FETCH(a0, 1) # a0 <- CCBB
4896 and a2, a0, 255 # a2 <- BB
4897 srl a3, a0, 8 # a3 <- CC
4900 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
4908 addu v0, a2, a0 # optional op
4909 addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed
4921 * subu v0,a0,a2
4923 * sltu a0,a0,v0
4924 * subu v1,v1,a0
4929 * specifies an instruction that performs "result = a0-a1 op a2-a3".
4931 * comes back in a register other than a0, you can override "result".)
4942 FETCH(a0, 1) # a0 <- CCBB
4944 and a2, a0, 255 # a2 <- BB
4945 srl a3, a0, 8 # a3 <- CC
4948 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
4956 subu v0, a0, a2 # optional op
4957 subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed
4969 * a1 a0
4979 FETCH(a0, 1) # a0 <- CCBB
4980 and t0, a0, 255 # a2 <- BB
4981 srl t1, a0, 8 # a3 <- CC
4983 LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1
4988 mul v1, a3, a0 # v1= a3a0
4990 mulu v0, a2, a0 # v0= a2a0
4991 muhu t1, a2, a0
4993 multu a2, a0
5001 GET_OPA(a0) # a0 <- AA
5012 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5014 * comes back in a register other than a0, you can override "result".)
5025 FETCH(a0, 1) # a0 <- CCBB
5027 and a2, a0, 255 # a2 <- BB
5028 srl a3, a0, 8 # a3 <- CC
5031 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
5040 JAL(__divdi3) # result <- op, a0-a3 changed
5053 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5055 * comes back in a register other than a0, you can override "result".)
5066 FETCH(a0, 1) # a0 <- CCBB
5068 and a2, a0, 255 # a2 <- BB
5069 srl a3, a0, 8 # a3 <- CC
5072 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
5081 JAL(__moddi3) # result <- op, a0-a3 changed
5094 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5096 * comes back in a register other than a0, you can override "result".)
5107 FETCH(a0, 1) # a0 <- CCBB
5109 and a2, a0, 255 # a2 <- BB
5110 srl a3, a0, 8 # a3 <- CC
5113 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
5121 and a0, a0, a2 # optional op
5122 and a1, a1, a3 # result <- op, a0-a3 changed
5124 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1
5135 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5137 * comes back in a register other than a0, you can override "result".)
5148 FETCH(a0, 1) # a0 <- CCBB
5150 and a2, a0, 255 # a2 <- BB
5151 srl a3, a0, 8 # a3 <- CC
5154 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
5162 or a0, a0, a2 # optional op
5163 or a1, a1, a3 # result <- op, a0-a3 changed
5165 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1
5176 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5178 * comes back in a register other than a0, you can override "result".)
5189 FETCH(a0, 1) # a0 <- CCBB
5191 and a2, a0, 255 # a2 <- BB
5192 srl a3, a0, 8 # a3 <- CC
5195 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
5203 xor a0, a0, a2 # optional op
5204 xor a1, a1, a3 # result <- op, a0-a3 changed
5206 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1
5221 FETCH(a0, 1) # a0 <- CCBB
5223 and a3, a0, 255 # a3 <- BB
5224 srl a0, a0, 8 # a0 <- CC
5226 GET_VREG(a2, a0) # a2 <- vCC
5227 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1
5233 sll v0, a0, a2 # rlo<- alo << (shift&31)
5236 srl a0, 1
5237 srl a0, v1 # alo<- alo >> (32-(shift&31))
5239 or v1, a0 # rhi<- rhi | alo
5240 SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- a0/a1
5253 FETCH(a0, 1) # a0 <- CCBB
5255 and a3, a0, 255 # a3 <- BB
5256 srl a0, a0, 8 # a0 <- CC
5258 GET_VREG(a2, a0) # a2 <- vCC
5259 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1
5266 srl v0, a0, a2 # rlo<- alo >> (shift&31)
5267 not a0, a2 # alo<- 31-shift (shift is 5b)
5269 sll a1, a0 # ahi<- ahi << (32-(shift&31))
5284 FETCH(a0, 1) # a0 <- CCBB
5286 and a3, a0, 255 # a3 <- BB
5287 srl a0, a0, 8 # a0 <- CC
5289 GET_VREG(a2, a0) # a2 <- vCC
5290 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1
5298 srl v0, a0, a2 # rlo<- alo >> (shift&31)
5299 not a0, a2 # alo<- 31-n (shift is 5b)
5301 sll a1, a0 # ahi<- ahi << (32-(shift&31))
5317 FETCH(a0, 1) # a0 <- CCBB
5319 srl a3, a0, 8 # a3 <- CC
5320 and a2, a0, 255 # a2 <- BB
5322 GET_VREG_F(fa0, a2) # a0 <- vBB
5343 FETCH(a0, 1) # a0 <- CCBB
5345 srl a3, a0, 8 # a3 <- CC
5346 and a2, a0, 255 # a2 <- BB
5348 GET_VREG_F(fa0, a2) # a0 <- vBB
5369 FETCH(a0, 1) # a0 <- CCBB
5371 srl a3, a0, 8 # a3 <- CC
5372 and a2, a0, 255 # a2 <- BB
5374 GET_VREG_F(fa0, a2) # a0 <- vBB
5395 FETCH(a0, 1) # a0 <- CCBB
5397 srl a3, a0, 8 # a3 <- CC
5398 and a2, a0, 255 # a2 <- BB
5400 GET_VREG_F(fa0, a2) # a0 <- vBB
5421 FETCH(a0, 1) # a0 <- CCBB
5423 srl a3, a0, 8 # a3 <- CC
5424 and a2, a0, 255 # a2 <- BB
5426 GET_VREG_F(fa0, a2) # a0 <- vBB
5442 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5450 FETCH(a0, 1) # a0 <- CCBB
5452 and a2, a0, 255 # a2 <- BB
5453 srl a3, a0, 8 # a3 <- CC
5472 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5480 FETCH(a0, 1) # a0 <- CCBB
5482 and a2, a0, 255 # a2 <- BB
5483 srl a3, a0, 8 # a3 <- CC
5502 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5510 FETCH(a0, 1) # a0 <- CCBB
5512 and a2, a0, 255 # a2 <- BB
5513 srl a3, a0, 8 # a3 <- CC
5532 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5540 FETCH(a0, 1) # a0 <- CCBB
5542 and a2, a0, 255 # a2 <- BB
5543 srl a3, a0, 8 # a3 <- CC
5562 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5570 FETCH(a0, 1) # a0 <- CCBB
5572 and a2, a0, 255 # a2 <- BB
5573 srl a3, a0, 8 # a3 <- CC
5592 * that specifies an instruction that performs "result = a0 op a1".
5605 GET_VREG(a0, rOBJ) # a0 <- vA
5614 addu a0, a0, a1 # a0 <- op, a0-a3 changed
5616 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5627 * that specifies an instruction that performs "result = a0 op a1".
5640 GET_VREG(a0, rOBJ) # a0 <- vA
5649 subu a0, a0, a1 # a0 <- op, a0-a3 changed
5651 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5662 * that specifies an instruction that performs "result = a0 op a1".
5675 GET_VREG(a0, rOBJ) # a0 <- vA
5684 mul a0, a0, a1 # a0 <- op, a0-a3 changed
5686 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5698 * that specifies an instruction that performs "result = a0 op a1".
5711 GET_VREG(a0, rOBJ) # a0 <- vA
5720 div a0, a0, a1 # a0 <- op, a0-a3 changed
5722 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5729 * that specifies an instruction that performs "result = a0 op a1".
5742 GET_VREG(a0, rOBJ) # a0 <- vA
5750 div zero, a0, a1 # optional op
5751 mflo a0 # a0 <- op, a0-a3 changed
5753 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5766 * that specifies an instruction that performs "result = a0 op a1".
5779 GET_VREG(a0, rOBJ) # a0 <- vA
5788 mod a0, a0, a1 # a0 <- op, a0-a3 changed
5790 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5797 * that specifies an instruction that performs "result = a0 op a1".
5810 GET_VREG(a0, rOBJ) # a0 <- vA
5818 div zero, a0, a1 # optional op
5819 mfhi a0 # a0 <- op, a0-a3 changed
5821 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5833 * that specifies an instruction that performs "result = a0 op a1".
5846 GET_VREG(a0, rOBJ) # a0 <- vA
5855 and a0, a0, a1 # a0 <- op, a0-a3 changed
5857 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5868 * that specifies an instruction that performs "result = a0 op a1".
5881 GET_VREG(a0, rOBJ) # a0 <- vA
5890 or a0, a0, a1 # a0 <- op, a0-a3 changed
5892 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5903 * that specifies an instruction that performs "result = a0 op a1".
5916 GET_VREG(a0, rOBJ) # a0 <- vA
5925 xor a0, a0, a1 # a0 <- op, a0-a3 changed
5927 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5938 * that specifies an instruction that performs "result = a0 op a1".
5951 GET_VREG(a0, rOBJ) # a0 <- vA
5960 sll a0, a0, a1 # a0 <- op, a0-a3 changed
5962 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5973 * that specifies an instruction that performs "result = a0 op a1".
5986 GET_VREG(a0, rOBJ) # a0 <- vA
5995 sra a0, a0, a1 # a0 <- op, a0-a3 changed
5997 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6008 * that specifies an instruction that performs "result = a0 op a1".
6021 GET_VREG(a0, rOBJ) # a0 <- vA
6030 srl a0, a0, a1 # a0 <- op, a0-a3 changed
6032 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6046 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6048 * comes back in a register other than a0, you can override "result".)
6063 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6070 addu v0, a2, a0 # optional op
6071 addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed
6088 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6090 * comes back in a register other than a0, you can override "result".)
6105 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6112 subu v0, a0, a2 # optional op
6113 subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed
6131 LOAD64(a0, a1, t0) # vAA.low / high
6137 mul v1, a3, a0 # v1= a3a0
6139 mulu v0, a2, a0 # v0= a2a0
6140 muhu t1, a2, a0
6142 multu a2, a0
6163 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6165 * comes back in a register other than a0, you can override "result".)
6180 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6188 JAL(__divdi3) # result <- op, a0-a3 changed
6202 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6204 * comes back in a register other than a0, you can override "result".)
6219 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6227 JAL(__moddi3) # result <- op, a0-a3 changed
6241 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6243 * comes back in a register other than a0, you can override "result".)
6258 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6265 and a0, a0, a2 # optional op
6266 and a1, a1, a3 # result <- op, a0-a3 changed
6268 SET_VREG64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1
6280 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6282 * comes back in a register other than a0, you can override "result".)
6297 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6304 or a0, a0, a2 # optional op
6305 or a1, a1, a3 # result <- op, a0-a3 changed
6307 SET_VREG64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1
6319 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6321 * comes back in a register other than a0, you can override "result".)
6336 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6343 xor a0, a0, a2 # optional op
6344 xor a1, a1, a3 # result <- op, a0-a3 changed
6346 SET_VREG64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1
6364 LOAD64(a0, a1, t2) # a0/a1 <- vAA/vAA+1
6370 sll v0, a0, a2 # rlo<- alo << (shift&31)
6373 srl a0, 1
6374 srl a0, v1 # alo<- alo >> (32-(shift&31))
6376 or v1, a0 # rhi<- rhi | alo
6377 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- a0/a1
6392 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6399 srl v0, a0, a2 # rlo<- alo >> (shift&31)
6400 not a0, a2 # alo<- 31-shift (shift is 5b)
6402 sll a1, a0 # ahi<- ahi << (32-(shift&31))
6404 SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- a0/a1
6419 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6427 srl v0, a0, a2 # rlo<- alo >> (shift&31)
6428 not a0, a2 # alo<- 31-n (shift is 5b)
6430 sll a1, a0 # ahi<- ahi << (32-(shift&31))
6432 SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/vAA+1 <- a0/a1
6441 * that specifies an instruction that performs "result = a0 op a1".
6467 * that specifies an instruction that performs "result = a0 op a1".
6493 * that specifies an instruction that performs "result = a0 op a1".
6519 * that specifies an instruction that performs "result = a0 op a1".
6545 * that specifies an instruction that performs "result = a0 op a1".
6571 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6599 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6627 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6655 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6683 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6711 * that specifies an instruction that performs "result = a0 op a1".
6713 * comes back in a register other than a0, you can override "result".)
6725 GET_VREG(a0, a2) # a0 <- vB
6734 addu a0, a0, a1 # a0 <- op, a0-a3 changed
6736 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6748 * that specifies an instruction that performs "result = a0 op a1".
6750 * comes back in a register other than a0, you can override "result".)
6762 GET_VREG(a0, a2) # a0 <- vB
6771 subu a0, a1, a0 # a0 <- op, a0-a3 changed
6773 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6784 * that specifies an instruction that performs "result = a0 op a1".
6786 * comes back in a register other than a0, you can override "result".)
6798 GET_VREG(a0, a2) # a0 <- vB
6807 mul a0, a0, a1 # a0 <- op, a0-a3 changed
6809 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6821 * that specifies an instruction that performs "result = a0 op a1".
6823 * comes back in a register other than a0, you can override "result".)
6835 GET_VREG(a0, a2) # a0 <- vB
6844 div a0, a0, a1 # a0 <- op, a0-a3 changed
6846 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6853 * that specifies an instruction that performs "result = a0 op a1".
6855 * comes back in a register other than a0, you can override "result".)
6867 GET_VREG(a0, a2) # a0 <- vB
6875 div zero, a0, a1 # optional op
6876 mflo a0 # a0 <- op, a0-a3 changed
6878 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6891 * that specifies an instruction that performs "result = a0 op a1".
6893 * comes back in a register other than a0, you can override "result".)
6905 GET_VREG(a0, a2) # a0 <- vB
6914 mod a0, a0, a1 # a0 <- op, a0-a3 changed
6916 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6923 * that specifies an instruction that performs "result = a0 op a1".
6925 * comes back in a register other than a0, you can override "result".)
6937 GET_VREG(a0, a2) # a0 <- vB
6945 div zero, a0, a1 # optional op
6946 mfhi a0 # a0 <- op, a0-a3 changed
6948 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6960 * that specifies an instruction that performs "result = a0 op a1".
6962 * comes back in a register other than a0, you can override "result".)
6974 GET_VREG(a0, a2) # a0 <- vB
6983 and a0, a0, a1 # a0 <- op, a0-a3 changed
6985 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6996 * that specifies an instruction that performs "result = a0 op a1".
6998 * comes back in a register other than a0, you can override "result".)
7010 GET_VREG(a0, a2) # a0 <- vB
7019 or a0, a0, a1 # a0 <- op, a0-a3 changed
7021 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7032 * that specifies an instruction that performs "result = a0 op a1".
7034 * comes back in a register other than a0, you can override "result".)
7046 GET_VREG(a0, a2) # a0 <- vB
7055 xor a0, a0, a1 # a0 <- op, a0-a3 changed
7057 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7068 * that specifies an instruction that performs "result = a0 op a1".
7070 * comes back in a register other than a0, you can override "result".)
7083 GET_VREG(a0, a2) # a0 <- vBB
7092 addu a0, a0, a1 # a0 <- op, a0-a3 changed
7094 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7105 * that specifies an instruction that performs "result = a0 op a1".
7107 * comes back in a register other than a0, you can override "result".)
7120 GET_VREG(a0, a2) # a0 <- vBB
7129 subu a0, a1, a0 # a0 <- op, a0-a3 changed
7131 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7142 * that specifies an instruction that performs "result = a0 op a1".
7144 * comes back in a register other than a0, you can override "result".)
7157 GET_VREG(a0, a2) # a0 <- vBB
7166 mul a0, a0, a1 # a0 <- op, a0-a3 changed
7168 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7180 * that specifies an instruction that performs "result = a0 op a1".
7182 * comes back in a register other than a0, you can override "result".)
7195 GET_VREG(a0, a2) # a0 <- vBB
7204 div a0, a0, a1 # a0 <- op, a0-a3 changed
7206 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7213 * that specifies an instruction that performs "result = a0 op a1".
7215 * comes back in a register other than a0, you can override "result".)
7228 GET_VREG(a0, a2) # a0 <- vBB
7236 div zero, a0, a1 # optional op
7237 mflo a0 # a0 <- op, a0-a3 changed
7239 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7252 * that specifies an instruction that performs "result = a0 op a1".
7254 * comes back in a register other than a0, you can override "result".)
7267 GET_VREG(a0, a2) # a0 <- vBB
7276 mod a0, a0, a1 # a0 <- op, a0-a3 changed
7278 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7285 * that specifies an instruction that performs "result = a0 op a1".
7287 * comes back in a register other than a0, you can override "result".)
7300 GET_VREG(a0, a2) # a0 <- vBB
7308 div zero, a0, a1 # optional op
7309 mfhi a0 # a0 <- op, a0-a3 changed
7311 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7323 * that specifies an instruction that performs "result = a0 op a1".
7325 * comes back in a register other than a0, you can override "result".)
7338 GET_VREG(a0, a2) # a0 <- vBB
7347 and a0, a0, a1 # a0 <- op, a0-a3 changed
7349 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7360 * that specifies an instruction that performs "result = a0 op a1".
7362 * comes back in a register other than a0, you can override "result".)
7375 GET_VREG(a0, a2) # a0 <- vBB
7384 or a0, a0, a1 # a0 <- op, a0-a3 changed
7386 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7397 * that specifies an instruction that performs "result = a0 op a1".
7399 * comes back in a register other than a0, you can override "result".)
7412 GET_VREG(a0, a2) # a0 <- vBB
7421 xor a0, a0, a1 # a0 <- op, a0-a3 changed
7423 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7434 * that specifies an instruction that performs "result = a0 op a1".
7436 * comes back in a register other than a0, you can override "result".)
7449 GET_VREG(a0, a2) # a0 <- vBB
7458 sll a0, a0, a1 # a0 <- op, a0-a3 changed
7460 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7471 * that specifies an instruction that performs "result = a0 op a1".
7473 * comes back in a register other than a0, you can override "result".)
7486 GET_VREG(a0, a2) # a0 <- vBB
7495 sra a0, a0, a1 # a0 <- op, a0-a3 changed
7497 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7508 * that specifies an instruction that performs "result = a0 op a1".
7510 * comes back in a register other than a0, you can override "result".)
7523 GET_VREG(a0, a2) # a0 <- vBB
7532 srl a0, a0, a1 # a0 <- op, a0-a3 changed
7534 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7551 lw a0, 0(t0) # a0 <- obj.field (8/16/32 bits)
7554 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0
7568 LOAD64(a0, a1, t0) # a0 <- obj.field (64 bits, aligned)
7571 SET_VREG64(a0, a1, a2) # fp[A] <- a0/a1
7583 GET_VREG(a0, a2) # a0 <- object we're operating on
7605 GET_VREG(a0, a2) # a0 <- fp[A]
7608 sw a0, 0(t0) # obj.field (8/16/32 bits) <- a0
7617 GET_OPA4(a0) # a0 <- A(+)
7622 EAS2(a3, rFP, a0) # a3 <- &fp[A]
7623 LOAD64(a0, a1, a3) # a0/a1 <- fp[A]
7626 addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1
7627 STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1
7638 addu a0, rFP, OFF_FP_SHADOWFRAME
7659 move a0, rSELF
7684 move a0, rSELF
7709 GET_VREG(a0, a2) # a0 <- fp[A]
7712 sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0
7729 GET_VREG(a0, a2) # a0 <- fp[A]
7732 sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0
7749 GET_VREG(a0, a2) # a0 <- fp[A]
7752 sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0
7769 GET_VREG(a0, a2) # a0 <- fp[A]
7772 sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0
7791 lbu a0, 0(t0) # a0 <- obj.field (8/16/32 bits)
7794 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0
7811 lb a0, 0(t0) # a0 <- obj.field (8/16/32 bits)
7814 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0
7831 lhu a0, 0(t0) # a0 <- obj.field (8/16/32 bits)
7834 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0
7851 lh a0, 0(t0) # a0 <- obj.field (8/16/32 bits)
7854 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0
8290 SET_VREG64(v0, v1, a0) # vAA::vAA+1 <- v0(low) :: v1(high)
8378 move a0, rSELF # arg0
8396 move a0, rSELF # arg0
8414 move a0, rSELF # arg0
8432 move a0, rSELF # arg0
8450 move a0, rSELF # arg0
8468 move a0, rSELF # arg0
8486 move a0, rSELF # arg0
8504 move a0, rSELF # arg0
8522 move a0, rSELF # arg0
8540 move a0, rSELF # arg0
8558 move a0, rSELF # arg0
8576 move a0, rSELF # arg0
8594 move a0, rSELF # arg0
8612 move a0, rSELF # arg0
8630 move a0, rSELF # arg0
8648 move a0, rSELF # arg0
8666 move a0, rSELF # arg0
8684 move a0, rSELF # arg0
8702 move a0, rSELF # arg0
8720 move a0, rSELF # arg0
8738 move a0, rSELF # arg0
8756 move a0, rSELF # arg0
8774 move a0, rSELF # arg0
8792 move a0, rSELF # arg0
8810 move a0, rSELF # arg0
8828 move a0, rSELF # arg0
8846 move a0, rSELF # arg0
8864 move a0, rSELF # arg0
8882 move a0, rSELF # arg0
8900 move a0, rSELF # arg0
8918 move a0, rSELF # arg0
8936 move a0, rSELF # arg0
8954 move a0, rSELF # arg0
8972 move a0, rSELF # arg0
8990 move a0, rSELF # arg0
9008 move a0, rSELF # arg0
9026 move a0, rSELF # arg0
9044 move a0, rSELF # arg0
9062 move a0, rSELF # arg0
9080 move a0, rSELF # arg0
9098 move a0, rSELF # arg0
9116 move a0, rSELF # arg0
9134 move a0, rSELF # arg0
9152 move a0, rSELF # arg0
9170 move a0, rSELF # arg0
9188 move a0, rSELF # arg0
9206 move a0, rSELF # arg0
9224 move a0, rSELF # arg0
9242 move a0, rSELF # arg0
9260 move a0, rSELF # arg0
9278 move a0, rSELF # arg0
9296 move a0, rSELF # arg0
9314 move a0, rSELF # arg0
9332 move a0, rSELF # arg0
9350 move a0, rSELF # arg0
9368 move a0, rSELF # arg0
9386 move a0, rSELF # arg0
9404 move a0, rSELF # arg0
9422 move a0, rSELF # arg0
9440 move a0, rSELF # arg0
9458 move a0, rSELF # arg0
9476 move a0, rSELF # arg0
9494 move a0, rSELF # arg0
9512 move a0, rSELF # arg0
9530 move a0, rSELF # arg0
9548 move a0, rSELF # arg0
9566 move a0, rSELF # arg0
9584 move a0, rSELF # arg0
9602 move a0, rSELF # arg0
9620 move a0, rSELF # arg0
9638 move a0, rSELF # arg0
9656 move a0, rSELF # arg0
9674 move a0, rSELF # arg0
9692 move a0, rSELF # arg0
9710 move a0, rSELF # arg0
9728 move a0, rSELF # arg0
9746 move a0, rSELF # arg0
9764 move a0, rSELF # arg0
9782 move a0, rSELF # arg0
9800 move a0, rSELF # arg0
9818 move a0, rSELF # arg0
9836 move a0, rSELF # arg0
9854 move a0, rSELF # arg0
9872 move a0, rSELF # arg0
9890 move a0, rSELF # arg0
9908 move a0, rSELF # arg0
9926 move a0, rSELF # arg0
9944 move a0, rSELF # arg0
9962 move a0, rSELF # arg0
9980 move a0, rSELF # arg0
9998 move a0, rSELF # arg0
10016 move a0, rSELF # arg0
10034 move a0, rSELF # arg0
10052 move a0, rSELF # arg0
10070 move a0, rSELF # arg0
10088 move a0, rSELF # arg0
10106 move a0, rSELF # arg0
10124 move a0, rSELF # arg0
10142 move a0, rSELF # arg0
10160 move a0, rSELF # arg0
10178 move a0, rSELF # arg0
10196 move a0, rSELF # arg0
10214 move a0, rSELF # arg0
10232 move a0, rSELF # arg0
10250 move a0, rSELF # arg0
10268 move a0, rSELF # arg0
10286 move a0, rSELF # arg0
10304 move a0, rSELF # arg0
10322 move a0, rSELF # arg0
10340 move a0, rSELF # arg0
10358 move a0, rSELF # arg0
10376 move a0, rSELF # arg0
10394 move a0, rSELF # arg0
10412 move a0, rSELF # arg0
10430 move a0, rSELF # arg0
10448 move a0, rSELF # arg0
10466 move a0, rSELF # arg0
10484 move a0, rSELF # arg0
10502 move a0, rSELF # arg0
10520 move a0, rSELF # arg0
10538 move a0, rSELF # arg0
10556 move a0, rSELF # arg0
10574 move a0, rSELF # arg0
10592 move a0, rSELF # arg0
10610 move a0, rSELF # arg0
10628 move a0, rSELF # arg0
10646 move a0, rSELF # arg0
10664 move a0, rSELF # arg0
10682 move a0, rSELF # arg0
10700 move a0, rSELF # arg0
10718 move a0, rSELF # arg0
10736 move a0, rSELF # arg0
10754 move a0, rSELF # arg0
10772 move a0, rSELF # arg0
10790 move a0, rSELF # arg0
10808 move a0, rSELF # arg0
10826 move a0, rSELF # arg0
10844 move a0, rSELF # arg0
10862 move a0, rSELF # arg0
10880 move a0, rSELF # arg0
10898 move a0, rSELF # arg0
10916 move a0, rSELF # arg0
10934 move a0, rSELF # arg0
10952 move a0, rSELF # arg0
10970 move a0, rSELF # arg0
10988 move a0, rSELF # arg0
11006 move a0, rSELF # arg0
11024 move a0, rSELF # arg0
11042 move a0, rSELF # arg0
11060 move a0, rSELF # arg0
11078 move a0, rSELF # arg0
11096 move a0, rSELF # arg0
11114 move a0, rSELF # arg0
11132 move a0, rSELF # arg0
11150 move a0, rSELF # arg0
11168 move a0, rSELF # arg0
11186 move a0, rSELF # arg0
11204 move a0, rSELF # arg0
11222 move a0, rSELF # arg0
11240 move a0, rSELF # arg0
11258 move a0, rSELF # arg0
11276 move a0, rSELF # arg0
11294 move a0, rSELF # arg0
11312 move a0, rSELF # arg0
11330 move a0, rSELF # arg0
11348 move a0, rSELF # arg0
11366 move a0, rSELF # arg0
11384 move a0, rSELF # arg0
11402 move a0, rSELF # arg0
11420 move a0, rSELF # arg0
11438 move a0, rSELF # arg0
11456 move a0, rSELF # arg0
11474 move a0, rSELF # arg0
11492 move a0, rSELF # arg0
11510 move a0, rSELF # arg0
11528 move a0, rSELF # arg0
11546 move a0, rSELF # arg0
11564 move a0, rSELF # arg0
11582 move a0, rSELF # arg0
11600 move a0, rSELF # arg0
11618 move a0, rSELF # arg0
11636 move a0, rSELF # arg0
11654 move a0, rSELF # arg0
11672 move a0, rSELF # arg0
11690 move a0, rSELF # arg0
11708 move a0, rSELF # arg0
11726 move a0, rSELF # arg0
11744 move a0, rSELF # arg0
11762 move a0, rSELF # arg0
11780 move a0, rSELF # arg0
11798 move a0, rSELF # arg0
11816 move a0, rSELF # arg0
11834 move a0, rSELF # arg0
11852 move a0, rSELF # arg0
11870 move a0, rSELF # arg0
11888 move a0, rSELF # arg0
11906 move a0, rSELF # arg0
11924 move a0, rSELF # arg0
11942 move a0, rSELF # arg0
11960 move a0, rSELF # arg0
11978 move a0, rSELF # arg0
11996 move a0, rSELF # arg0
12014 move a0, rSELF # arg0
12032 move a0, rSELF # arg0
12050 move a0, rSELF # arg0
12068 move a0, rSELF # arg0
12086 move a0, rSELF # arg0
12104 move a0, rSELF # arg0
12122 move a0, rSELF # arg0
12140 move a0, rSELF # arg0
12158 move a0, rSELF # arg0
12176 move a0, rSELF # arg0
12194 move a0, rSELF # arg0
12212 move a0, rSELF # arg0
12230 move a0, rSELF # arg0
12248 move a0, rSELF # arg0
12266 move a0, rSELF # arg0
12284 move a0, rSELF # arg0
12302 move a0, rSELF # arg0
12320 move a0, rSELF # arg0
12338 move a0, rSELF # arg0
12356 move a0, rSELF # arg0
12374 move a0, rSELF # arg0
12392 move a0, rSELF # arg0
12410 move a0, rSELF # arg0
12428 move a0, rSELF # arg0
12446 move a0, rSELF # arg0
12464 move a0, rSELF # arg0
12482 move a0, rSELF # arg0
12500 move a0, rSELF # arg0
12518 move a0, rSELF # arg0
12536 move a0, rSELF # arg0
12554 move a0, rSELF # arg0
12572 move a0, rSELF # arg0
12590 move a0, rSELF # arg0
12608 move a0, rSELF # arg0
12626 move a0, rSELF # arg0
12644 move a0, rSELF # arg0
12662 move a0, rSELF # arg0
12680 move a0, rSELF # arg0
12698 move a0, rSELF # arg0
12716 move a0, rSELF # arg0
12734 move a0, rSELF # arg0
12752 move a0, rSELF # arg0
12770 move a0, rSELF # arg0
12788 move a0, rSELF # arg0
12806 move a0, rSELF # arg0
12824 move a0, rSELF # arg0
12842 move a0, rSELF # arg0
12860 move a0, rSELF # arg0
12878 move a0, rSELF # arg0
12896 move a0, rSELF # arg0
12914 move a0, rSELF # arg0
12932 move a0, rSELF # arg0
12950 move a0, rSELF # arg0
12968 move a0, rSELF # arg0
12995 move a0, rSELF
13004 move a0, rSELF
13013 move a0, rSELF
13022 move a0, rSELF
13031 move a0, rSELF
13040 move a0, rSELF
13049 move a0, rSELF
13062 lw a0, THREAD_EXCEPTION_OFFSET(rSELF)
13063 beqz a0, MterpFallback # If exception, fall back to reference interpreter.
13071 move a0, rSELF
13075 lw a0, OFF_FP_CODE_ITEM(rFP)
13078 addu rPC, a0, CODEITEM_INSNS_OFFSET
13103 move a0, rSELF
13114 move a0, rSELF
13128 move a0, rSELF
