Lines Matching full:fifo
47 #define UART_FCR 2 /* Out: FIFO Control Register */
48 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
49 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
50 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
53 * Note: The FIFO trigger levels are chip specific:
75 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
132 #define UART_LSR_FIFOE 0x80 /* Fifo error */
192 * In: Fifo count
193 * Out: Fifo custom trigger levels */
239 #define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */
240 #define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */
241 #define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */
242 #define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */
248 #define UART_RFL 0x03 /* Receiver FIFO level */
249 #define UART_TFL 0x04 /* Transmitter FIFO level */
292 #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
298 #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
299 #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
300 #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
306 #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
307 #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
308 #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
309 #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
310 #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
311 #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
315 #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
347 #define UART_OMAP_TX_LVL 0x1a /* TX FIFO level register */
371 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
372 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
373 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
374 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
376 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
377 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
