Lines Matching refs:UWORD32
63 UWORD32 num_4x4_dst;
64 UWORD32 num_4x4;
65 UWORD32 num_8x8;
66 UWORD32 num_16x16;
67 UWORD32 num_32x32;
68 UWORD32 num_64x64;
74 UWORD32 trans_4x4_dst[1];
75 UWORD32 trans_4x4[1];
76 UWORD32 trans_8x8[4];
77 UWORD32 trans_16x16[16];
78 UWORD32 trans_32x32[64];
84 UWORD32 trans_4x4_dst[16];
85 UWORD32 trans_4x4[16];
86 UWORD32 trans_8x8[64];
87 UWORD32 trans_16x16[256];
88 UWORD32 trans_32x32[1024];
100 UWORD32 stat_pu_all_size_hist[16][16]; /* PU Sizes [Width from 4 to 64 in steps of 4] [Height from 4 to 64 in steps of 4]*/
101 UWORD32 stat_pu_skip_size_hist[16][16]; /* PU sizes for skip [Width from 4 to 64 in steps of 4] [Height from 4 to 64 in steps of 4]*/
102 UWORD32 stat_pu_inter_size_hist[16][16]; /* PU sizes for inter [Width from 4 to 64 in steps of 4] [Height from 4 to 64 in steps of 4]*/
103 UWORD32 stat_pu_intra_size_hist[16][16]; /* PU sizes for intra [Width from 4 to 64 in steps of 4] [Height from 4 to 64 in steps of 4]*/
104 UWORD32 stat_pu_bipred_size_hist[16][16]; /* PU sizes for bipred [Width from 4 to 64 in steps of 4] [Height from 4 to 64 in steps of 4]*/
105 UWORD32 stat_pu_merge_size_hist[16][16]; /* PU sizes for merge [Width from 4 to 64 in steps of 4] [Height from 4 to 64 in steps of 4]*/
106 UWORD32 stat_pu_zeromv_size_hist[16][16]; /* PU sizes for Zero MV [Width from 4 to 64 in steps of 4] [Height from 4 to 64 in steps of 4]*/
107 UWORD32 stat_pu_zeromvfpel_size_hist[16][16]; /* PU sizes for Zero MV (includes subpel less than +/- 1 full pel units [Width from 4 to 64 in steps of 4] [Height from 4 to 64 in steps of 4]*/
108 UWORD32 last_sblk_pos_x; /* Last sblk pos of transform block in processing */
109 UWORD32 last_sblk_pos_y;
110 UWORD32 num_coded_sblk;
111 UWORD32 num_coded_coeffs;
118 void ihevcd_sblk_pos_update(TRANSFORM_TYPE e_trans_type, WORD32 t_skip_or_tq_bypass, UWORD32 sblk_x, UWORD32 sblk_y);
