Home | History | Annotate | Download | only in CodeGen

Lines Matching refs:VirtRegI

136     VirtRegI = VirtReg->begin();
138 LiveUnionI.find(VirtRegI->start);
144 assert(VirtRegI != VirtRegEnd && "Reached end of VirtReg");
147 while (VirtRegI->start < LiveUnionI.stop() &&
148 VirtRegI->end > LiveUnionI.start()) {
165 // beyond VirtRegI.
166 assert(VirtRegI->end <= LiveUnionI.start() && "Expected non-overlap");
169 VirtRegI = VirtReg->advanceTo(VirtRegI, LiveUnionI.start());
170 if (VirtRegI == VirtRegEnd)
174 if (VirtRegI->start < LiveUnionI.stop())
178 LiveUnionI.advanceTo(VirtRegI->start);