Lines Matching refs:Intf
267 InterferenceCache::Cursor Intf;
276 Intf.setPhysReg(Cache, Reg);
751 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
752 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) &&
755 if (getStage(*Intf) == RS_Done)
764 (Intf->isSpillable() ||
766 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
768 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
777 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
780 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
787 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
792 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
793 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) {
828 LiveInterval *Intf = Intfs[i];
830 if (!VRM->hasPhys(Intf->reg))
832 Matrix->unassign(*Intf);
833 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
834 VirtReg.isSpillable() < Intf->isSpillable()) &&
836 ExtraRegInfo[Intf->reg].Cascade = Cascade;
838 NewVRegs.push_back(Intf->reg);
932 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
944 Intf.moveToBlock(BC.Number);
949 if (!Intf.hasInterference())
957 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
959 else if (Intf.first() < BI.FirstInstr)
961 else if (Intf.first() < BI.LastInstr)
967 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
969 else if (Intf.last() > BI.LastInstr)
971 else if (Intf.last() > BI.FirstInstr)
990 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
999 Intf.moveToBlock(Number);
1001 if (!Intf.hasInterference()) {
1015 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
1021 if (Intf.last() >= SA->getLastSplitPoint(Number))
1073 addThroughConstraints(Cand.Intf, NewBlocks);
1107 // The static split cost will be zero since Cand.Intf reports no interference.
1109 if (!addSplitConstraints(Cand.Intf, Cost)) {
1180 Cand.Intf.moveToBlock(Number);
1181 if (Cand.Intf.hasInterference()) {
1231 Cand.Intf.moveToBlock(Number);
1232 IntfIn = Cand.Intf.first();
1240 Cand.Intf.moveToBlock(Number);
1241 IntfOut = Cand.Intf.last();
1280 Cand.Intf.moveToBlock(Number);
1281 IntfIn = Cand.Intf.first();
1288 Cand.Intf.moveToBlock(Number);
1289 IntfOut = Cand.Intf.last();
1411 if (!addSplitConstraints(Cand.Intf, Cost)) {
2015 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
2016 // If Intf is done and sit on the same register class as VirtReg,
2018 if ((getStage(*Intf) == RS_Done &&
2019 MRI->getRegClass(Intf->reg) == CurRC) ||
2020 FixedRegisters.count(Intf->reg)) {
2024 RecoloringCandidates.insert(Intf);
