Lines Matching refs:ScheduleDAGRRList
1 //===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
109 /// ScheduleDAGRRList - The actual register reduction list scheduler
112 class ScheduleDAGRRList : public ScheduleDAGSDNodes {
162 ScheduleDAGRRList(MachineFunction &mf, bool needlatency,
176 ~ScheduleDAGRRList() override {
320 void ScheduleDAGRRList::Schedule() {
365 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
525 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) {
570 void ScheduleDAGRRList::ReleasePending() {
600 void ScheduleDAGRRList::AdvanceToCycle(unsigned NextCycle) {
622 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) {
664 void ScheduleDAGRRList::EmitNode(SUnit *SU) {
706 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
791 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
805 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
892 void ScheduleDAGRRList::RestoreHazardCheckerBottomUp() {
913 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) {
946 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
1144 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
1268 bool ScheduleDAGRRList::
1345 void ScheduleDAGRRList::releaseInterferences(unsigned Reg) {
1374 SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() {
1499 void ScheduleDAGRRList::ListScheduleBottomUp() {
1644 ScheduleDAGRRList *scheduleDAG;
1680 void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
2720 ScheduleDAGRRList *scheduleDAG,
3002 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
3016 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
3032 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
3047 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
