Lines Matching full:divisor
7376 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
7382 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
7387 unsigned Lg2 = Divisor.countTrailingZeros();
7409 if (Divisor.isNonNegative())
9877 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
