Lines Matching refs:TVal
1685 SDValue TVal = Sel.getOperand(2);
1694 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1703 std::swap(TVal, FVal);
1714 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1717 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1772 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1779 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
3829 SDValue TVal = DAG.getConstant(1, dl, VT);
3853 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3872 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3882 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3885 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3890 SDValue RHS, SDValue TVal,
3919 // If both the TVal and the FVal are constants, see if we can swap them in
3922 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3925 std::swap(TVal, FVal);
3929 std::swap(TVal, FVal);
3932 } else if (TVal.getOpcode() == ISD::XOR) {
3933 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3935 if (isAllOnesConstant(TVal.getOperand(1))) {
3936 std::swap(TVal, FVal);
3940 } else if (TVal.getOpcode() == ISD::SUB) {
3941 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3943 if (isNullConstant(TVal.getOperand(0))) {
3944 std::swap(TVal, FVal);
3953 // If both TVal and FVal are constants, see if FVal is the
3954 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3960 } else if (TVal.getValueType() == MVT::i32) {
3985 // Swap TVal and FVal if necessary.
3987 std::swap(TVal, FVal);
3994 // TVal.
3995 FVal = TVal;
4002 EVT VT = TVal.getValueType();
4003 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
4009 EVT VT = TVal.getValueType();
4017 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
4023 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
4035 SDValue TVal = Op.getOperand(2);
4038 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4044 SDValue TVal = Op->getOperand(1);
4063 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
4079 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
