Lines Matching refs:MBB
38 const MachineBasicBlock &MBB = *MI->getParent();
39 const MachineFunction *MF = MBB.getParent();
92 bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
99 if (I == MBB.end())
110 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
134 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
146 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
220 unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
221 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
222 if (I == MBB.end())
232 I = MBB.end();
234 if (I == MBB.begin())
246 MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB,
250 BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
255 BuildMI(&MBB, DL, get(Cond[1].getImm())).addOperand(Cond[2]);
263 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
270 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB);
272 instantiateCondBranch(MBB, DL, TBB, Cond);
277 instantiateCondBranch(MBB, DL, TBB, Cond);
278 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB);
361 const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond,
365 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
401 void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
406 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
443 BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR)
449 BuildMI(MBB, I, DL, get(AArch64::SUBSWri), AArch64::WZR)
472 BuildMI(MBB, I, DL, get(AArch64::ANDSWri), AArch64::WZR)
477 BuildMI(MBB, I, DL, get(AArch64::ANDSXri), AArch64::XZR)
531 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm(
707 MachineBasicBlock *MBB = Instr->getParent();
708 assert(MBB && "Can't get MachineBasicBlock here");
709 MachineFunction *MF = MBB->getParent();
970 for (auto *MBB : ParentBlock->successors())
971 MBB->isLiveIn(AArch64::NZCV))
990 MachineBasicBlock &MBB = *MI->getParent();
995 const TargetMachine &TM = MBB.getParent()->getTarget();
1000 BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg)
1002 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1006 BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
1008 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1011 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1014 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1017 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1021 BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg)
1024 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1030 MBB.erase(MI);
1524 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
1542 const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
1549 void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1569 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestRegX)
1575 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
1581 BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg).addImm(0).addImm(
1594 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestRegX)
1600 BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
1612 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
1617 BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg).addImm(0).addImm(
1621 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
1633 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1643 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1652 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1662 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1672 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1681 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1689 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1693 BuildMI(MBB, I, DL, get(AArch64::STRQpre))
1698 BuildMI(MBB, I, DL, get(AArch64::LDRQpre))
1714 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1718 BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
1731 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1735 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1748 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1756 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1769 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1777 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1786 BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg)
1792 BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
1799 BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg)
1805 BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
1812 BuildMI(MBB, I, DL, get(AArch64::MSR))
1821 BuildMI(MBB, I, DL, get(AArch64::MRS))
1832 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
1836 if (MBBI != MBB.end())
1838 MachineFunction &MF = *MBB.getParent();
1920 const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc))
1930 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
1934 if (MBBI != MBB.end())
1936 MachineFunction &MF = *MBB.getParent();
2018 const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc))
2026 void llvm::emitFrameOffset(MachineBasicBlock &MBB,
2066 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
2077 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
2464 static bool canCombineWithMUL(MachineBasicBlock &MBB, MachineOperand &MO,
2466 MBB.getParent()->getRegInfo();
2472 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != MulOpc)
2500 MachineBasicBlock &MBB = *Root.getParent();
2524 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2529 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDWrrr,
2536 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2541 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDXrrr,
2548 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2553 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDWrrr,
2560 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2565 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDXrrr,
2572 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2579 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2586 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr,
2593 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr,
2706 MachineBasicBlock &MBB = *Root.getParent();
2707 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2708 MachineFunction &MF = *MBB.getParent();
2947 MachineBasicBlock *MBB = MI->getParent();
2948 MachineFunction *MF = MBB->getParent();
2976 MachineBasicBlock &RefToMBB = *MBB;
