Lines Matching full:writev
302 def : WriteRes<WriteV, [CyUnitV]> {let Latency = 2;}
325 // MOVI,MVNI are WriteV
326 // FMOVv2f32ns,FMOVv2f64ns,FMOVv4f32ns are WriteV
333 SchedVar<NoSchedPred, [WriteV]>]>;
338 // MOV V,V is a WriteV.
340 // CPY D,V[x] is a WriteV
342 // INS V[x],V[y] is a WriteV.
353 def CyWriteCopyToFPR : WriteSequence<[WriteVLD, WriteV]>;
363 // DUP V,V[x] is a WriteV.
369 // BIC,ORR V,#imm are WriteV
373 // MVN,NEG,NOT are WriteV
377 // ADDP is a WriteV.
386 // ADD,SUB are WriteV
408 // WriteV includes:
469 // SHL is a WriteV
484 // SSHL,USHL are WriteV.
488 // SQSHL,SQSHLU,UQSHL are WriteV.
492 // WriteV includes:
569 def : InstRW<[WriteV], (instrs FCVTSHr,FCVTDHr,FCVTDSr)>;
584 // FCVTL is a WriteV
602 // TRN,UZP,ZUP are WriteV.
604 // TBL,TBX are WriteV.
679 def : InstRW<[WriteVLDShuffle, WriteV],
681 def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV],
688 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV],
690 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV],
692 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV],
694 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV],
697 def : InstRW<[WriteVLDShuffle, WriteV],
699 def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV],
702 def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV],
704 def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV],
711 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV, WriteV],
713 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV, WriteV],
716 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVLDShuffle, WriteV],
718 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVLDShuffle, WriteV],
721 def : InstRW<[WriteVLDShuffle, WriteV, WriteV],
723 def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV, WriteV],
726 def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV],
728 def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV],
731 def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV, WriteV],
733 def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV, WriteV],
742 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV, WriteV, WriteV],
744 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV, WriteV, WriteV],
748 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVLDShuffle, WriteV, WriteV],
750 def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVLDShuffle, WriteV],
753 def : InstRW<[WriteVLDShuffle, WriteV, WriteV, WriteV],
755 def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV, WriteV, WriteV],
758 def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV, WriteV],
760 def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV, WriteV],
