Lines Matching refs:Name
57 bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
60 unsigned matchRegisterNameAlias(StringRef Name, bool isVector);
81 bool parseDirectiveReq(StringRef Name, SMLoc L);
89 /// @name Auto-generated Match Functions
130 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1796 StringRef Name = getBarrierName();
1797 if (!Name.empty())
1798 OS << "<barrier " << Name << ">";
1840 StringRef Name = getPrefetchName();
1841 if (!Name.empty())
1842 OS << "<prfop " << Name << ">";
1862 /// @name Auto-generated Match Functions
1865 static unsigned MatchRegisterName(StringRef Name);
1869 static unsigned matchVectorRegName(StringRef Name) {
1870 return StringSwitch<unsigned>(Name.lower())
1906 static bool isValidVectorKind(StringRef Name) {
1907 return StringSwitch<bool>(Name.lower())
1929 static void parseValidVectorKind(StringRef Name, unsigned &NumElements,
1931 assert(isValidVectorKind(Name));
1933 ElementKind = Name.lower()[Name.size() - 1];
1936 if (Name.size() == 2)
1940 Name = Name.drop_front();
1941 while (isdigit(Name.front())) {
1942 NumElements = 10 * NumElements + (Name.front() - '0');
1943 Name = Name.drop_front();
1955 // Matches a register name or register alias previously defined by '.req'
1956 unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
1958 unsigned RegNum = isVector ? matchVectorRegName(Name)
1959 : MatchRegisterName(Name);
1965 auto Entry = RegisterReqs.find(Name.lower());
1975 /// tryParseRegister - Try to parse a register name. The token must be an
1976 /// Identifier when called, and if it is a register name the token is eaten and
2001 /// tryMatchVectorRegister - Try to parse a vector register name with optional
2010 StringRef Name = Parser.getTok().getString();
2011 // If there is a kind specifier, it's separated from the register name by
2013 size_t Start = 0, Next = Name.find('.');
2014 StringRef Head = Name.slice(Start, Next);
2019 Kind = Name.slice(Next, StringRef::npos);
2034 /// tryParseSysCROperand - Try to parse a system instruction CR operand name.
2092 StringRef Name =
2094 Operands.push_back(AArch64Operand::CreatePrefetch(prfop, Name,
2474 bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
2476 if (Name.find('.') != StringRef::npos)
2479 Mnemonic = Name;
2746 // Can be either a #imm style literal or an option name
2767 StringRef Name =
2769 Operands.push_back( AArch64Operand::CreateBarrier(MCE->getValue(), Name,
2784 TokError("invalid barrier option name");
3196 // If it's a register name, parse it.
3318 StringRef Name, SMLoc NameLoc,
3321 Name = StringSwitch<StringRef>(Name.lower())
3340 .Default(Name);
3345 parseDirectiveReq(Name, NameLoc);
3352 size_t Start = 0, Next = Name.find('.');
3353 StringRef Head = Name.slice(Start, Next);
3370 Next = Name.find('.', Start + 1);
3371 Head = Name.slice(Start + 1, Next);
3374 (Head.data() - Name.data()));
3387 Next = Name.find('.', Start + 1);
3388 Head = Name.slice(Start, Next);
3390 Name.data()) + 1);
4289 StringRef Name;
4290 if (getParser().parseIdentifier(Name))
4293 MCSymbol *Sym = getContext().getOrCreateSymbol(Name);
4321 StringRef Name = getTok().getIdentifier();
4324 int Id = MCLOHNameToId(Name);
4339 StringRef Name;
4340 if (getParser().parseIdentifier(Name))
4342 Args.push_back(getContext().getOrCreateSymbol(Name));
4365 /// ::= name .req registername
4366 bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
4385 Error(SRegLoc, "register name or alias expected");
4399 if (RegisterReqs.insert(std::make_pair(Name, pair)).first->second != pair)
4400 Warning(L, "ignoring redefinition of register alias '" + Name + "'");
