Lines Matching refs:MBB
312 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
368 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
375 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
380 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32))
389 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
411 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
460 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
539 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
545 MachineFunction *MF = MBB.getParent();
548 DebugLoc DL = MBB.findDebugLoc(MI);
565 BuildMI(MBB, MI, DL, get(Opcode))
577 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
587 BuildMI(MBB, MI, DL, get(Opcode))
629 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
634 MachineFunction *MF = MBB.getParent();
637 DebugLoc DL = MBB.findDebugLoc(MI);
651 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
662 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
670 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
678 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
683 MachineFunction *MF = MBB.getParent();
688 DebugLoc DL = MBB.findDebugLoc(MI);
694 MachineBasicBlock &Entry = MBB.getParent()->front();
769 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
791 MachineBasicBlock &MBB = *MI->getParent();
792 DebugLoc DL = MBB.findDebugLoc(MI);
811 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
814 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
819 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
822 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
838 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
842 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
853 MachineFunction &MF = *MBB.getParent();
860 MIBundleBuilder Bundler(MBB, MI);
872 llvm::finalizeBundle(MBB, Bundler.begin());
1014 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
1018 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
1251 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1271 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1681 MachineBasicBlock *MBB = MI->getParent();
1683 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1700 DebugLoc DL = MBB->findDebugLoc(I);
1713 MachineBasicBlock *MBB = MI->getParent();
1718 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1729 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1732 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
2030 MachineBasicBlock *MBB = MI->getParent();
2048 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
2067 MachineBasicBlock &MBB = *MI->getParent();
2069 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
2092 MachineBasicBlock &MBB = *MI->getParent();
2106 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
2111 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2116 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2121 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc)
2139 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
2144 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
2149 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2157 assert(MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration()
2174 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2200 Addr64 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2217 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2240 MachineBasicBlock *MBB = MI->getParent();
2241 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2255 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
2261 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
2270 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
2272 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2277 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
2285 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
2289 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
2292 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2330 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDst)
2340 MachineBasicBlock *MBB = MI->getParent();
2360 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2366 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2370 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2384 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2386 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2388 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2390 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2408 BuildMI(*MBB, MI, MI->getDebugLoc(), NewInstDesc, NewDstReg)
2451 MachineBasicBlock *MBB = Inst->getParent();
2452 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2625 MachineBasicBlock &MBB = *Inst->getParent();
2626 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2635 BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg)
2639 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
2651 MachineBasicBlock &MBB = *Inst->getParent();
2652 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2675 BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2682 BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2686 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2705 MachineBasicBlock &MBB = *Inst->getParent();
2706 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2737 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2747 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2752 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2771 MachineBasicBlock &MBB = *Inst->getParent();
2772 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2795 BuildMI(MBB, MII, DL, InstDesc, MidReg)
2799 BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2812 MachineBasicBlock &MBB = *Inst->getParent();
2813 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2835 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2840 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2844 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2859 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2863 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2981 MachineBasicBlock *MBB,
2985 const DebugLoc &DL = MBB->findDebugLoc(I);
2987 getIndirectIndexBegin(*MBB->getParent()));
2989 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2999 MachineBasicBlock *MBB,
3003 const DebugLoc &DL = MBB->findDebugLoc(I);
3005 getIndirectIndexBegin(*MBB->getParent()));
3007 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC_V1))
