Lines Matching refs:SRC
566 .addReg(SrcReg) // src
588 .addReg(SrcReg) // src
1277 .addImm(0) // Src mods
1982 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1992 SRC = OpRC;
2001 assert(SRC);
2002 VRC = RI.getEquivalentVGPRClass(SRC);
2006 RC = SRC;
2631 MachineOperand &Src = Inst->getOperand(1);
2637 .addReg(Src.getReg());
2640 .addReg(Src.getReg())
2778 MachineOperand &Src = Inst->getOperand(1);
2781 const TargetRegisterClass *SrcRC = Src.isReg() ?
2782 MRI.getRegClass(Src.getReg()) :
2790 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2792 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2855 MachineOperand &Src = Inst->getOperand(1);
2861 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2864 .addReg(Src.getReg(), 0, AMDGPU::sub0)
