Lines Matching refs:VCC
94 // is vcc. We should handle this the same way we handle vopc, by addding
253 // VOPC instructions can only write to the VCC register. We can't
254 // force them to use VCC here, because this is only one register and
256 // VCC, e.g. S_AND_B64 (vcc = V_CMP_...), (vcc = V_CMP_...)
258 // So, instead of forcing the instruction to write to VCC, we provide
259 // a hint to the register allocator to use VCC and then we we will run
260 // this pass again after RA and shrink it if it outputs to VCC.
261 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);
264 if (DstReg != AMDGPU::VCC)
277 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC);
280 if (SReg != AMDGPU::VCC)
291 // For VOPC instructions, this is replaced by an implicit def of vcc.
297 assert(MI.getOperand(0).getReg() == AMDGPU::VCC &&
317 // replaced with an implicit read of vcc.
318 assert(Src2->getReg() == AMDGPU::VCC &&
