Lines Matching refs:MBB
278 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
285 MachineBasicBlock::iterator I = MBB.end();
286 if (I == MBB.begin())
301 if (I == MBB.begin())
346 while (DI != MBB.end()) {
357 if (I == MBB.begin())
369 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
370 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
371 if (I == MBB.end())
381 I = MBB.end();
383 if (I == MBB.begin()) return 1;
394 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
398 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
415 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
417 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
419 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
425 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
428 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
430 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
598 const MachineBasicBlock &MBB = *MI->getParent();
599 const MachineFunction *MF = MBB.getParent();
659 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
668 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
680 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
688 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
702 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
710 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
731 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
790 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
793 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
818 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
846 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
851 if (I != MBB.end()) DL = I->getDebugLoc();
852 MachineFunction &MF = *MBB.getParent();
863 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
867 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
875 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
880 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
890 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
902 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
907 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
919 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
925 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
940 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
946 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
960 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
1035 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1040 if (I != MBB.end()) DL = I->getDebugLoc();
1041 MachineFunction &MF = *MBB.getParent();
1051 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1055 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1062 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1068 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1077 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1091 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1095 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1105 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1110 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1125 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1130 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1146 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1407 reMaterialize(MachineBasicBlock &MBB,
1415 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1417 MBB.insert(I, MI);
1422 MachineFunction &MF = *MBB.getParent();
1425 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1657 const MachineBasicBlock *MBB,
1680 while (++I != MBB->end() && I->isDebugValue())
1682 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1700 isProfitableToIfCvt(MachineBasicBlock &MBB,
1709 if (MBB.getParent()->getFunction()->optForSize()) {
1710 MachineBasicBlock *Pred = *MBB.pred_begin();
1996 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
2002 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2024 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2611 MachineBasicBlock *MBB = CmpInstr->getParent();
2612 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2613 SE = MBB->succ_end(); SI != SE; ++SI)
4087 MachineBasicBlock &MBB = *MI->getParent();
4094 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4098 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4101 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4102 MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 4, 4);
4107 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
